Scalable integrated circuit high density capacitors
View Patent ↗The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
1. A capacitor, comprising:
a first, second, and third metal layer, each including a first metallization pattern and a second metallization pattern, the first and second metallization patterns each having a plurality of interdigitated finger tracks approximately perpendicular to a respective backbone track,
wherein a finger track in the plurality of finger tracks in the second metal layer is offset relative to a corresponding one of the finger tracks in the plurality of finger tracks in the first metal layer, and
wherein the first metallization patterns in the first and third metal layers are electrically coupled to the second metallization pattern in the second metal layer.
2. The capacitor of claim 1 , wherein the second metallization patterns in the first and third metal layers are electrically coupled to the first metallization pattern in the second metal layer.
3. The capacitor of claim 1 , wherein a portion of a finger track in the pluralities of finger tracks in the first and second metallization patterns in the first metal layer overlaps a portion of a finger track in the pluralities of finger tracks in the first and second metallization patterns in the second metal layer.
4. The capacitor of claim 1 , wherein a central axis of a finger track in the plurality of finger tracks in the second metal layer is substantially equidistant from both respective central axes of two finger tracks, adjacent to the finger track in the plurality of finger tracks in the second metal layer, in the plurality of finger tracks in the first metal layer.
5. The capacitor of claim 1 , wherein an end of the backbone track in the first metallization pattern in the first metal layer is electrically coupled to a wire, and wherein a finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer, extending from a non-distal and non-proximal portion of the backbone track in the first metallization pattern in the first metal layer, does not completely overlap any finger tracks in the plurality of finger tracks in the second metal layer.
6. The capacitor of claim 5 , wherein all finger tracks extending from a non-distal, non-proximal portion of the backbone track in the first metallization pattern in the first metal layer, do not completely overlap any finger track in the second metal layer.
7. The capacitor of claim 1 , wherein the backbone track in the first metallization pattern in the first metal layer is an interdigitated element of a third metallization pattern.
8. The capacitor of claim 1 , wherein at least one of the first and second metallization patterns in the first metal layer is electrically coupled to a shield.
9. The capacitor of claim 8 , wherein the shield is a side shield.
10. The capacitor of claim 8 , wherein the shield is a bottom shield.
11. The capacitor of claim 1 , wherein a finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer is wider than a distance between the finger track, in the plurality of finger tracks in the first metallization pattern in the first metal layer, and an adjacent finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer.
12. The capacitor of claim 1 , wherein a finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer is narrower than a distance between the finger track, in the plurality of finger tracks in the first metallization pattern in the first metal layer, and an adjacent finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer.
13. The capacitor of claim 1 , wherein the plurality of finger tracks in the first metallization pattern in the first metal layer are staggered with respect to the plurality of finger tracks in the first metallization pattern in the second metal layer.
14. The capacitor of claim 1 , wherein the finger track in the plurality of finger tracks in the second metal layer is offset by more than one-half of a width of the finger track relative to the corresponding one of the finger tracks in the plurality of finger tracks in the first metal layer.
15. A capacitor, comprising:
a first, second, and third metal layer, each including a first metallization pattern and a second metallization pattern, the first and second metallization patterns each having a plurality of interdigitated finger tracks approximately perpendicular to a respective backbone track,
wherein a finger track in the plurality of finger tracks in the second metal layer is offset by more than one-half of a width of the finger track relative to a corresponding one of the finger tracks of the plurality of finger tracks in the first metal layer,
wherein the first metallization patterns in the first and third metal layers are electrically coupled to the second metallization pattern in the second metal layer,
wherein the second metallization patterns in the first and third metal layers are electrically coupled to the first metallization pattern in the second metal layer,
wherein a portion of a finger track in the pluralities of finger tracks in the first and second metallization patterns in the first metal layer overlaps a portion of a finger track in the pluralities of finger tracks in the first and second metallization patterns in the second metal layer,
wherein an end of the backbone track in the first metallization pattern in the first metal layer is electrically coupled to a wire,
wherein a finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer, extending from a non-distal and non-proximal portion of the backbone track in the first metallization pattern in the first metal layer, does not completely overlap any finger tracks in the plurality of finger tracks in the second metal layer,
wherein the backbone track in the first metallization pattern in the first metal layer is an interdigitated element of a third metallization pattern,
wherein at least one of the first and second metallization patterns in the first metal layer is electrically coupled to a side shield, and
wherein a finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer is wider than a distance between the finger track, in the plurality of finger tracks in the first metallization pattern in the first metal layer, and an adjacent finger track in the plurality of finger tracks in the first metallization pattern in the first metal layer.