Semiconductor device and method for producing the same
View Patent ↗First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r 1 ′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r 1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r 1 . The radius of curvature r 2 ′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r 2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r 2.
1. A semiconductor device comprising:
a first fin-shaped semiconductor region formed on a substrate, the first fin-shaped semiconductor region having first-conductivity-type impurity region formed therein;
a second fin-shaped semiconductor region formed on the substrate, the second fin-shaped semiconductor region having second-conductivity-type impurity region formed therein;
a first gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first fin-shaped semiconductor region, the upper corner of the first fin-shaped semiconductor region having a radius of curvature of r 1 under the first gate insulating film different from a radius of curvature of r 1 ′ outside the first gate insulating film; and
a second gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the second fin-shaped semiconductor region, the upper corner of the second fin-shaped semiconductor region having a radius of curvature of r 2 under the second gate insulating film different from a radius of curvature of r 2 ′ outside the second gate insulating film, wherein
r 1 ′ is greater than r 1 and less than or equal to 2×r 1 , and
r 2 ′ is greater than r 2 and less than or equal to 2×r 2 .
2. The semiconductor device of claim 1 , wherein
the first-conductivity type impurity region includes a first first-conductivity-type impurity region formed in an upper portion of the first fin-shaped semiconductor regions and a second first-conductivity-type impurity region formed in a side portion of the first fin-shaped semiconductor region, and
the second-conductivity-type impurity region includes a first second-conductivity-type impurity region formed in an upper portion of the second fin-shaped semiconductor region and a second second-conductivity-type impurity region formed in a side portion of the second fin-shaped semiconductor region.
3. The semiconductor device of claim 2 , wherein
a sheet resistance of the second first-conductivity-type impurity region is less than or equal to 1.25 times that of the first first-conductivity-type impurity region, and
a sheet resistance of the second second-conductivity-type impurity region is less than or equal to 1.25 times that of the first second-conductivity-type impurity region.
4. The semiconductor device of claim 2 , wherein
a resistivity of the second first-conductivity-type impurity region is less than or equal to 1.25 times that of the first first-conductivity-type impurity region, and
a resistivity of the second second-conductivity-type impurity region is less than or equal to 1.25 times that of the first second-conductivity-type impurity region.
5. The semiconductor device of claim 2 , wherein
a spreading resistance of the second first-conductivity-type impurity region is less than or equal to 1.25 times that of the first first-conductivity-type impurity region, and
a spreading resistance of the second second-conductivity-type impurity region is less than or equal to 1.25 times that of the first second-conductivity-type impurity region.
6. The semiconductor device of claim 2 , wherein
a junction depth of the second first-conductivity-type impurity region is substantially equal to or greater than that of the first first-conductivity-type impurity region, and
a junction depth of the second second-conductivity-type impurity region is substantially equal to or greater than that of the first second-conductivity-type impurity region.
7. The semiconductor device of claim 2 , further comprising:
a first gate electrode formed on the first gate insulating film; and
a second gate electrode formed on the second gate insulating film, wherein
the first first-conductivity-type impurity region and the second first-conductivity-type impurity region are formed in another portion of the first fin-shaped semiconductor region other than the predetermined portion, and
the first second-conductivity-type impurity region and the second second-conductivity-type impurity region are formed in another portion of the second fin-shaped semiconductor region other than the predetermined portion.
8. The semiconductor device of claim 7 , wherein
the first gate insulating film is formed also on an upper surface of the predetermined portion of the first fin-shaped semiconductor region, and
the second gate insulating film is formed also on an upper surface of the predetermined portion of the second fin-shaped semiconductor region.
9. The semiconductor device of claim 7 , wherein
the first first-conductivity-type impurity region and the second first-conductivity-type impurity region are p-type extension regions, and
the first second-conductivity-type impurity region and the second second-conductivity-type impurity region are n-type extension regions.
10. The semiconductor device of claim 7 , further comprising:
a first insulative sidewall spacer formed on a side surface of the first gate electrode;
a second insulative sidewall spacer formed on a side surface of the second gate electrode;
a third first-conductivity-type impurity region formed in the upper portion of the first fin-shaped semiconductor region;
a fourth first-conductivity-type impurity region formed in the side portion of the first fin-shaped semiconductor region;
a third second-conductivity-type impurity region formed in the upper portion of the second fin-shaped semiconductor region; and
a fourth second-conductivity-type impurity region formed in the side portion of the second fin-shaped semiconductor region, wherein
the third first-conductivity-type impurity region and the fourth first-conductivity-type impurity region are formed in a portion of the other portion of the first fin-shaped semiconductor region that is located outside the first insulative sidewall spacer, and
the third second-conductivity-type impurity region and the fourth second-conductivity-type impurity region are formed in a portion of the other portion of the second fin-shaped semiconductor region that is located outside the second insulative sidewall spacer.
11. The semiconductor device of claim 10 , wherein
the third first-conductivity-type impurity region and the fourth first-conductivity-type impurity region are p-type source-drain regions, and
the third second-conductivity-type impurity region and the fourth second-conductivity-type impurity region are n-type source-drain regions.
12. The semiconductor device of claim 1 , wherein
an insulating film is formed between the substrate and each of the first fin-shaped semiconductor region and the second fin-shaped semiconductor region.
13. The semiconductor device of claim 1 , wherein
a height of a side surface of the first fin-shaped semiconductor region is greater than a width in a gate width direction of an upper surface of the first fin-shaped semiconductor region, and
a height of a side surface of the second fin-shaped semiconductor region is greater than a width in a gate width direction of an upper surface of the second fin-shaped semiconductor region.
14. The semiconductor device of claim 1 , wherein
a width in a gate width direction of an upper surface of each of the first fin-shaped semiconductor region and the second fin-shaped semiconductor region is less than or equal to 20 nm.