Liquid crystal display panel and display device having the display panel
View Patent ↗A display panel includes a gate driving circuit, a plurality of gate lines, a plurality of data lines and a dummy gate line. The gate driving circuit is disposed in a peripheral area surrounding a display area. The gate lines are disposed in the display area and receive a plurality of gate signals sequentially outputted from the gate driving circuit. The data lines are disposed in the display area and cross the gate lines. The dummy gate line is disposed adjacent to the last gate line of the gate lines and receives a dummy gate signal transmitted from an external device. Thus, a dummy gate line is adjacent to the last gate line and a pixel electrode connected to the last gate line is affected by a dummy gate signal applied to the dummy gate line.
1. A display panel comprising:
a gate driving circuit disposed in a peripheral area surrounding a display area;
a plurality of gate lines disposed in the display area and configured to receive a gate signal outputted from the gate driving circuit, the gate signal comprising a first voltage and a second voltage, and the gate driving circuit being configured to sequentially transmit the first voltage of the gate signal to the plurality of gate lines;
a plurality of data lines disposed in the display area crossing the gate lines;
a dummy gate line disposed adjacent to a last gate line of the plurality of gate lines and configured to receive a dummy gate signal transmitted from an external device; and
a connection line electrically connected to the dummy gate line and configured to transmit the dummy gate signal to the dummy gate line,
wherein the gate driving circuit comprises a plurality of stages serially connected to each other, wherein a first stage of the plurality of stages is configured to receive a first vertical start signal starting a driving of the plurality of gate lines, and a last stage of the plurality of stages is configured to receive a second vertical start signal stopping the driving of the plurality of gate lines, and
wherein the dummy gate signal is the second vertical start signal.
2. The display panel of claim 1 , wherein the dummy gate signal comprises a third voltage and a fourth voltage, and levels of the third voltage and the fourth voltage are substantially the same as those of the first voltage and the second voltage, respectively.
3. The display panel of claim 1 , wherein the gate driving circuit comprises:
a first gate driving part having a plurality of odd-numbered stages serially connected to each other, the first gate driving part connected to a plurality of odd-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the odd-numbered gate lines; and
a second gate driving part having a plurality of even-numbered stages serially connected to each other, the second gate driving part connected to a plurality of even-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the even-numbered gate lines.
4. A display panel comprising:
a gate driving circuit disposed in a peripheral area surrounding a display area;
a plurality of gate lines disposed in the display area and configured to receive a gate signal outputted from the gate driving circuit, the gate signal comprising a first voltage and a second voltage, and the gate driving circuit being configured to sequentially transmit the first voltage of the gate signal to the plurality of gate lines;
a plurality of data lines disposed in the display area crossing the gate lines; and
a dummy gate line disposed adjacent to a last gate line of the plurality of gate lines and configured to receive a dummy gate signal transmitted from an external device,
wherein the gate driving circuit comprises:
a first gate driving part having a plurality of odd-numbered stages serially connected to each other, the first gate driving part connected to a plurality of odd-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the odd-numbered gate lines; and
a second gate driving part having a plurality of even-numbered stages serially connected to each other, the second gate driving part connected to a plurality of even-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the even-numbered gate lines,
wherein a first stage of the odd-numbered stages is configured to receive a first vertical start signal starting a driving of the odd-numbered gate lines, and a last stage of the odd-numbered stages is configured to receive a second vertical start signal stopping the driving of the gate lines of the odd-numbered stage, a first stage of the even-numbered stages is configured to receive a third vertical start signal starting a driving of the even-numbered gate lines, and a last stage of the even-numbered stages is configured to receive a fourth vertical start signal stopping the driving of the gate lines of the even-numbered stage, and the dummy gate signal is the second vertical start signal.
5. A display device comprising:
a display panel comprising a display area and a peripheral area surrounding the display area, the display area having a plurality of gate lines, a plurality of data lines crossing the gate lines, and a dummy gate line disposed adjacent to a last gate line of the plurality of gate lines, the dummy gate line being configured to receive a dummy gate signal transmitted from an external device;
a gate driving circuit integrated in the peripheral area and configured to output a gate signal to the gate lines, the gate signal comprising a first voltage and a second voltage, and the gate driving circuit being configured to sequentially output the first voltage of the gate signal to the gate lines; and
a data driving circuit configured to output a plurality of data signals to the data lines,
wherein the display panel further comprises a connection line electrically connected to the dummy gate line and configured to transmit the dummy gate signal to the dummy gate line,
wherein the gate driving circuit comprises a plurality of stages serially connected to each other, wherein a first stage of the plurality of stages is configured to receive a first vertical start signal starting a driving of the plurality of gate lines, and a last stage of the plurality of stages is configured to receive a second vertical start signal stopping the driving of the plurality of gate lines, and
wherein the dummy gate signal is the second vertical start signal.
6. The display device of claim 5 , wherein a last gate line of the plurality of the gate lines is configured to receive a last first voltage of the gate signal outputted from the gate driving circuit.
7. The display device of claim 5 , wherein the gate driving circuit comprises:
a first gate driving part having a plurality of odd-numbered stages serially connected to each other, the first gate driving part being connected to a plurality of odd-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the odd-numbered gate lines; and
a second gate driving part having a plurality of even-numbered stages serially connected to each other, the second gate driving part being connected to a plurality of even-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the even-numbered gate lines.
8. The display device of claim 7 , wherein a first stage of the odd-numbered stages is configured to receive a first vertical start signal starting a driving of the odd-numbered gate lines, and a last stage of the odd-numbered stages is configured to receive a second vertical start signal stopping the driving of the gate lines of the odd-numbered stage, a first stage of the even-numbered stages is configured to receive a third vertical start signal starting a driving of the even-numbered gate lines, and a last stage of the even-numbered stages is configured to receive a fourth vertical start signal stopping the driving of the gate lines of the even-numbered stage.
9. The display device of claim 8 , wherein the third vertical start signal is configured to be delayed for one horizontal cycle with respect to the first vertical start signal.
10. The display device of claim 8 , wherein the dummy gate signal is the second vertical start signal.
11. The display device of claim 8 , wherein a last gate line of the plurality of gate lines is configured to receive a last first voltage of gate signal outputted from the first gate driving part.
12. The display device of claim 8 , wherein the odd-numbered stages are integrated in a first peripheral area corresponding to a first terminal of the plurality of gate lines, and the even-numbered stages are integrated in a second peripheral area corresponding to a second terminal of the plurality of gate lines.
13. The display device of claim 8 , wherein the odd-numbered stages are configured to receive a first clock signal and a second clock signal having a phase opposite to the first clock signal, and the even-numbered stages are configured to receive a third clock signal delayed for one horizontal cycle with respect to the first clock signal and a fourth clock signal having a phase opposite to the third clock signal.
14. A display device comprising:
a display panel comprising a display area and a peripheral area surrounding the display area, the display area having a plurality of gate lines, a plurality of data lines crossing the gate lines, and a dummy gate line disposed adjacent to a last gate line of the plurality of gate lines, the dummy gate line being configured to receive a dummy gate signal transmitted from an external device;
a gate driving circuit integrated in the peripheral area and configured to output a gate signal to the gate lines, the gate signal comprising a first voltage and a second voltage, and the gate driving circuit being configured to sequentially output the first voltage of the gate signal to the gate lines; and
a data driving circuit configured to output a plurality of data signals to the data lines,
wherein the gate driving circuit comprises:
a first gate driving part having a plurality of odd-numbered stages serially connected to each other, the first gate driving part being connected to a plurality of odd-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the odd-numbered gate lines; and
a second gate driving part having a plurality of even-numbered stages serially connected to each other, the second gate driving part being connected to a plurality of even-numbered gate lines of the plurality of gate lines and being configured to output the gate signal to the even-numbered gate lines,
wherein a first stage of the odd-numbered stages is configured to receive a first vertical start signal starting a driving of the odd-numbered gate lines, and a last stage of the odd-numbered stages is configured to receive a second vertical start signal stopping the driving of the gate lines of the odd-numbered stage, a first stage of the even-numbered stages is configured to receive a third vertical start signal starting a driving of the even-numbered gate lines, and a last stage of the even-numbered stages is configured to receive a fourth vertical start signal stopping the driving of the gate lines of the even-numbered stage, and
wherein the dummy gate signal is the second vertical start signal.
15. The display device of claim 14 , wherein the display panel further comprises a connection line electrically connected to the dummy gate line and configured to transmit the dummy gate signal to the dummy gate line.
16. The display device of claim 15 , wherein the gate driving circuit comprises a plurality of stages serially connected to each other, wherein a first stage of the plurality of stages is configured to receive a first vertical start signal starting a driving of the plurality of gate lines, and a last stage of the plurality of stages is configured to receive a second vertical start signal stopping the driving of the plurality of gate lines.
17. The display device of claim 16 , wherein the dummy gate signal is the second vertical start signal.
18. The display device of claim 14 , wherein a last gate line of the plurality of the gate lines is configured to receive a last first voltage of the gate signal outputted from the gate driving circuit.
19. The display device of claim 14 , wherein the third vertical start signal is configured to be delayed for one horizontal cycle with respect to the first vertical start signal.
20. The display device of claim 14 , wherein a last gate line of the plurality of gate lines is configured to receive a last first voltage of gate signal outputted from the first gate driving part.
21. The display device of claim 14 , wherein the odd-numbered stages are integrated in a first peripheral area corresponding to a first terminal of the plurality of gate lines, and the even-numbered stages are integrated in a second peripheral area corresponding to a second terminal of the plurality of gate lines.
22. The display device of claim 14 , wherein the odd-numbered stages are configured to receive a first clock signal and a second clock signal having a phase opposite to the first clock signal, and the even-numbered stages are configured to receive a third clock signal delayed for one horizontal cycle with respect to the first clock signal and a fourth clock signal having a phase opposite to the third clock signal.