Integrated circuit to encode data
An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.
1. An integrated circuit configurable to encode data according to one of a predetermined plurality of coding schemes comprising block, convolutional and turbo codes and to generate cyclic redundancy codes, said integrated circuit comprising:
a) a plurality of specific hardware cells, each cell comprising:
outputs S ij , FO ij , BO ij and TO ij for binary signals,
inputs E ij , BI ij , FI ij and TI ij for binary signals,
a buffer to delay by one clock period a binary value received on input E ij and to output a one-clock period delayed binary value E*,
binary adders to perform XOR operations,
configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, the characteristic equations of the cell being:
TO ij =S ij =Ctm·TI ij +!Ctm ·Output Mux 4
Output Mux 4= Cmm 0 ·Cmm 1 ·E*+!Cmm 0 ·Cmm 1·( E*XORBI ij )+ Cmm 0 ·!Cmm 1 ·E+!Cmm 0 ·!Cmm 1·( E ij XORFI ij )
BO ij =Cbm ·( S ij XORBI ij )+! Cbm·BI ij
or
BO ij =Cbm 0 ·Cbm 1·( S ij XORBI ij )+! Cbm 0 ·Cbm 1 ·BI ij +!Cbm 0 ·Cbm 1 ·S ij
FO ij =Cfm ·( S ij XORFI ij )+! Cfm·FI ij
where:
S ij , FO ij , BO ij and TO ij are the binary signals output on outputs S ij , FO ij , BO ij and TO ij , respectively,
E ij , BI ij , FI ij and TI ij are the binary signals received on inputs E ij , BI ij , FI ij and TI ij , respectively,
“!” is the NOT operation,
“*” is the output of the buffer,
“XOR” is the XOR operation,
“+” is the OR operation,
“·” is the AND operation,
Cbm, Cbm0, Cbm1, Cfm, Cmm0, Cmm1 and Ctm are respective binary values that represent the configuration of each multiplexer,
b) controllable switch matrices external to each cell and able:
to electrically connect and, alternatively, to electrically disconnect input E ij to/from at least the output S ij of another cell and to electrically connect and, alternately, to electrically disconnect input E ij to/from an external binary data source,
to electrically connect and, alternately, to electrically disconnect at least input FI ij to/from at least the output FO ij of another cell,
to connect and, alternately, to disconnect input to/from at least the output BO ij of another cell.
2. An integrated circuit configurable to encode data according to one of a predetermined plurality of coding schemes comprising block, convolutional and turbo codes and to generate cyclic redundancy codes, said integrated circuit comprising:
a) a plurality of specific hardware cells, each cell comprising:
outputs S ij , FO ij , and BO ij for binary signals,
inputs E ij , BI ij , and FI ij for binary signals,
a buffer to delay by one clock period a binary value received on input E ij and to output a one-clock period delayed binary value E*,
binary adders to perform XOR operations,
configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, the characteristic equations of the cell being:
S ij =!Ctm ·Output Mux 4
Output Mux 4= Cmm 0 ·Cmm 1 ·E*+!Cmm 0 ·Cmm 1·( E*XORBI ij )+ Cmm 0 ·!Cmm 1 ·E+!Cmm 0 ·!Cmm 1·( E ij XORFI ij )
BO ij =Cbm ·( S ij XORBI ij )+! Cbm·BI ij
or
BO ij =Cbm 0· Cbm 1·( S ij XORBI ij )+! Cbm 0 ·Cbm 1 ·BI ij +!Cbm 0 ·Cbm 1· S ij
FO ij =Cfm ·( S ij XORFI ij )+! Cfm·FI ij
where:
S ij , FO ij and BO ij are the binary signals output on outputs S ij , FO ij and BO ij , respectively,
E ij , BI ij and FI ij are the binary signals received on inputs E ij , BI ij and FI ij , respectively,
“!” is the NOT operation,
“*” is the output of the buffer;
“XOR” is the XOR operation,
“+” is the OR operation,
“·” is the AND operation,
Cbm, Cbm0, Cbm1, Cfm, Cmm0, and Cmm1 are respective binary values that represent the configuration of each multiplexer,
b) controllable switch matrices external to each cell and able:
to electrically connect and, alternatively, to electrically disconnect input E ij to/from at least the output S ij of another cell and to electrically connect and, alternately, to electrically disconnect input E ij to/from an external binary data source,
to electrically connect and, alternately, to electrically disconnect at least input FI ij to/from at least the output FO ij of another cell,
to connect and, alternately, to disconnect input BI ij to/from at least the output BO ij of another cell.
3. The integrated circuit according to claim 2 , wherein the integrated circuit comprises a plurality of clusters CL j , each cluster CL j comprising:
inputs E j , FI j and BI j ,
outputs S j , BO j and FO j ,
a succession of at least two cells C ij successively electrically connected to each other, the first cell of the succession having its inputs and FI ij and its output BO ij directly connected to inputs E j , FI j and output BO j without configuration possibility, respectively,
the last cell of the succession having its input and its outputs S ij and FO ij connected, without configuration possibility to input BI j , outputs S j and FO j , respectively, and
any cell other than the last cell having its input BI 1 and its outputs S ij and FO ij connected, without any configuration possibility, to output BO ij and inputs E ij and FI ij of the following cell of the succession, respectively, and
wherein the switch matrix is only able to configure the electrical connections between cluster inputs and outputs without being able to configure the electrical connections between cells within a cluster.
4. The integrated circuit according to claim 3 , wherein the outputs S j , FO j and the input BI j of at least one cluster are connected to inputs E j , FI j and output BO j of another cluster without configuration possibility, respectively.
5. The integrated circuit according to claim 3 , wherein the integrated circuit comprises between five to ten clusters and each cluster is composed of five cells.
6. The integrated circuit according to claim 3 , wherein each cluster has at least one cell having the following characteristic equation:
BO ij =Cbm 0 ·Cbm 1·( S ij XORBI ij )+! Cbm 0 ·Cbm 1 BI ij +!Cbm 0 ·Cbm 1 ·S ij .
7. The integrated circuit according to claim 3 , wherein the inputs TI ij of the succession of cells of a cluster, are directly connected to respective outputs TO ij of the succession of cells of another cluster without any configuration possibility.
8. The integrated circuit according to claim 3 , wherein a cluster CL j comprises an input AI i and an adder having an first input directly connected to input AI j , a second input and an output, the second input and the output of the adder being:
either connected to output FO ij of the last cell and to output FO j , respectively,
or connected to output S ij of the last cell and to output S j , respectively.
9. A hardware cell optimized for use in an integrated circuit encoder comprising:
a first input E ij , a second input BI ij , a third input FI ij and a fourth input TI ij , each of said first, second, third and fourth inputs being for binary signals,
a first output S ij , a second output FO ij , a third output BO ij and a fourth output TO ij , each of said first, second, third and fourth outputs being for binary signals;
a buffer BU j having an input connected to said first input E ij and an output generating a binary value E*;
a first adder A 1i having a first input and a second input respectively coupled to the output of said buffer BU j and to said second input BI ij , said first adder A 1i having an output;
a second adder A 2i having a first input coupled to said second input BI ij , a second input and having further an output;
a third adder A 3i having a first input and a second input respectively coupled to said first input E ij and said third input FI ij , said third adder A 3i , having an output;
a fourth adder A 4j having a first input connected to said third input FI ij a second input and further having an output;
a first multiplexer MM having a first, a second, a third and a fourth input respectively coupled to the output of said buffer, to the output of said first adder A 1i , to said first input E ij and to the output of said third adder A 3i , and having an output connected to anyone of its inputs depending on the contents of a cell configuration register;
a second multiplexer TM having a first and a second input respectively coupled the output of said first multiplexer MM and said fourth input TI ij , and having an output connected to anyone of its inputs depending on the contents of said configuration register and being further coupled to said second input of said second adder A 2i , to the second input of said fourth adder A 4i and to said fourth output TO ij ,
a third multiplexer BM having a first and a second input respectively coupled to the output of said second adder A 2i and said second input BI ij , and having an output coupled to said third output BO ij and being connected to anyone of its inputs depending on the contents of said cell configuration register;
a fourth multiplexer FM having a first and a second input respectively coupled to said third input FI ij and to the output of said fourth adder A 4i , and having an output coupled to said second output FO ij and connected to an one of its inputs depending on the contents of said cell configuration register.
10. An integrated circuit encoder comprising:
a plurality of hardware cells in electrical communication as defined in claim 9 ; and
a programmable switch matrix coupled to the plurality of hardware cells.
11. The integrated circuit encoder of claim 10 wherein the switch matrix is only able to configure electrical connections between inputs and outputs of a cluster of hardware cells without being able to configure the electrical connections between hardware cells within a cluster of hardware cells.
12. The integrated circuit encoder of claim 10 configured to provide convolutional encoding operations that comply with any one of the following standards: GSM, UMTS, DMB, CDMA 2000, iDEN (Integrated Digital Enhanced Network), PHS (Personal Handy-phone System), PDC (Personal Digital Cellular), WPAN, WLAN, WMAN, or DVB (Digital Video Broadcasting).
13. The integrated circuit encoder of claim 10 configured to provide turbo encoding operations that comply with any one of the following standards: UMTS, SDMB (Satellite Digital Multimedia Broadcasting), CDMA 2000, or WMAN.
14. The integrated circuit encoder of claim 10 configured to provide randomization and scrambling operations that comply with any one of the following standards: UMTS, CDMA 2000, WMAN, WLAN, DMB, DAB, or DVB.
15. The integrated circuit encoder of claim 10 configured to provide a spreading process.