Nonvolatile semiconductor memory apparatus and manufacturing method thereof

1. A nonvolatile semiconductor memory apparatus comprising:

a substrate;

stripe-shaped lower-layer electrode wires provided on the substrate;

an interlayer insulating layer which is disposed on the substrate including the lower-layer electrode wires and is provided with contact holes at locations respectively opposite to the lower-layer electrode wires;

resistance variable layers which are respectively connected to the lower-layer electrode wires; and

non-ohmic devices which are respectively provided on the resistance variable layers such that the non-ohmic devices are respectively connected to the resistance variable layers; wherein

the non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer; and wherein

one layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

2. The nonvolatile semiconductor memory apparatus according to claim 1 , wherein a plurality of constituent units, each of which includes the interlayer insulating layer, the resistance variable layer, and the non-ohmic device, are stacked to form a layer structure.

3. The nonvolatile semiconductor memory apparatus according to claim 1 , wherein the other layers of the laminated-layer structures respectively forming the non-ohmic devices are provided in stripe shape on the interlayer insulating layer so as to respectively cross the lower-layer electrode wires.

4. The nonvolatile semiconductor memory apparatus according to claim 1 , further comprising:

stripe-shaped upper-layer electrode wires which are provided on the non-ohmic devices such that the upper-layer electrode wires are respectively connected to the non-ohmic devices and respectively cross the lower-layer electrode wires.

5. The nonvolatile semiconductor memory apparatus according to claim 1 , wherein the non-ohmic devices are MIM diodes each having a laminated-layer structure including three layers which are an insulator layer and metal electrode layers sandwiching the insulator layer, and the metal electrode layer which is closer to the resistance variable layer is embedded to fill each of the contact holes.

6. The nonvolatile semiconductor memory apparatus according to claim 1 , wherein the non-ohmic devices are MSM diodes each having a laminated-layer structure including three layers which are a semiconductor layer and metal electrode layers sandwiching the semiconductor layer, and the metal electrode layer which is closer to the resistance variable layer is embedded to fill each of the contact holes.

7. The nonvolatile semiconductor memory apparatus according to claim 1 , wherein the non-ohmic devices are p-n junction diodes each having a laminated-layer structure including two layers which are a p-type semiconductor layer and an n-type semiconductor layer, and the p-type semiconductor layer or the n-type semiconductor layer is embedded to fill each of the contact holes.

8. The nonvolatile semiconductor memory apparatus according to claim 1 , wherein the non-ohmic devices are schottky diodes each having a laminated-layer structure including two layers which are a semiconductor layer and a metal electrode layer, and the metal electrode layer is embedded to fill each of the contact holes.