Semiconductor storage device

1. A semiconductor storage device comprising:

a phase change thin film having two stable phases of a crystal state having a first resistance value and an amorphous state having a resistance value higher than the first resistance value;

first and second electrodes provided on one side of the phase change thin film;

a third electrode provided on the other side of the phase change thin film;

a first transistor whose drain terminal is connected to the first electrode, whose source terminal is connected to the third electrode, and whose gate terminal is connected to a first word line; and

a second transistor whose drain terminal is connected to the second electrode, whose source terminal is connected to the third electrode, and whose gate terminal is connected to a second word line, wherein

a first memory cell is configured with the first transistor and a first phase change region in the phase change thin film sandwiched between the first electrode and the third electrode,

a second memory cell is configured with the second transistor and a second phase change region in the phase change thin film sandwiched between the second electrode and the third electrode,

at a writing time to the first memory cell, the first transistor is turned off to carry a current from the first electrode to the third electrode, and

at a writing time to the second memory cell, the second transistor is turned off to carry a current from the second electrode to the third electrode.

2. The semiconductor storage device according to claim 1 ,

further comprising a current controlling transistor connected to the first memory cell and the second memory cell in series.

3. The semiconductor storage device according to claim 2 , wherein

a plurality of the first and second memory cells are repetitively connected in series, and

if it is assumed that the number of memory cells connected in series in a memory cell array is N,

an ON resistance R ON and an OFF resistance R OFF of a transistor configuring the memory cell, a resistance value R reset when the phase change thin film configuring the memory cell is in an amorphous state, and a resistance value R set when the phase change thin film is in a crystal state satisfy a condition of

( N− 1)×(R ON 2 /R OFF )×((R OFF +R set )/(R ON +R set ))<10×R reset .

4. The semiconductor storage device according to claim 1 , wherein

at a reading time, only the transistor of one selected from the memory cells is turned off, and the transistor of the unselected memory cell is turned on, so that a reading voltage is applied to both the electrodes of one selected from the phase change regions to read data of the selected memory cell, and

at a writing time, only the transistor of one selected from the memory cells is turned off, and the transistor of the unselected memory cell is turned on, so that a writing voltage is applied to both the electrodes of one selected from the phase change regions to apply a writing current to the selected phase change region.

5. The semiconductor storage device according to claim 1 , wherein

when the writing to one selected from the memory cells is performed, the writings to the adjacent memory cells in the memory cells connected in series are performed by applying currents with mutually reverse polarities.

6. The semiconductor storage device according to claim 1 , wherein

such an arrangement is formed that a plurality of memory cell arrays in which the same number of memory cells are connected in series are disposed, and that word lines in a direction perpendicular to the memory cell arrays, and the memory cells to be written and read are selected according to a combination of the memory cell arrays and the word lines.

7. The semiconductor storage device according to claim 6 , wherein

when information is written in the first memory cell, the first transistor is turned to an off state via the first word line connected to a gate electrode of the first transistor configuring the selected first memory cell, and a first current pulse is applied to the memory cell array including the selected first memory cell and connected in series so that the writing is performed, and

when a writing is performed to the second memory cell adjacent to the first memory cell via the second word line adjacent to the first word line, a second current pulse having a reverse direction to that of the first current pulse is applied to the cell array including the first and second memory cells.

8. The semiconductor storage device according to claim 1 , wherein

when a reading of one selected from the memory cells is performed,

a pulse always having a same condition to all the memory cells to be read is used for a reading voltage applied to both ends of one of the memory cells connected in series.

9. A semiconductor storage device comprising:

a plurality of word lines;

a plurality of bit lines intersecting with the plurality of word lines;

a plurality of memory cells arranged at the intersections of the plurality of word lines and the plurality of bit lines and each including a transistor and a storage device whose resistance changes according to storage information;

a plurality of hierarchy switches each arranged between the plurality of word lines at a constant interval;

a common data line;

a switch circuit arranged between the plurality of bit lines and the common data line and for selecting one of the plurality of bit lines to connect the one to the common data line; and

a rewriting circuit connected to the common data line, wherein

a first hierarchy switch of the plurality of hierarchy switches is inserted between a first bit line of the plurality of bit lines and a first memory cell of the plurality of memory cells and between a ground voltage terminal and the first memory cell, and a second hierarchy switch of the plurality of the hierarchy switches is inserted between the first bit line and a second memory cell of the plurality of memory cells and between the ground voltage terminal and the second memory cell.

10. The semiconductor storage device according to claim 9 , wherein

when the first bit line and the first memory cell are connected to each other by the first hierarchy switch, and when the ground voltage terminal and the second memory cell are connected to each other by the second hierarchy switch, a current flows in the first and second memory cells in a first direction, and

when the ground voltage terminal and the first memory cell are connected to each other by the first hierarchy switch, and when the first bit line and the second memory cell are connected to each other by the second hierarchy switch, a current flows in the first and second memory cells in a second direction, and

directions of the first current and the second current are reverse to each other.

11. The semiconductor storage device according to claim 10 , wherein

the storage device and the transistor are connected in parallel in each of the plurality of memory cells.

12. The semiconductor storage device according to claim 11 , wherein

the storage device is a material containing a chalcogenide material.

13. A semiconductor storage device comprising:

a first phase change thin film having two stable phases of a crystal state having a first resistance value and an amorphous state having a resistance value higher than the first resistance value;

a first electrode provided on one side of the first phase change thin film;

a second electrode provided on the other side of the first phase change thin film;

a first transistor whose drain terminal is connected to the first electrode, whose source terminal is connected to the second electrode, and whose gate terminal is connected to a first word line;

a second phase change thin film having two stable phases of the crystal state having the first resistance value and the amorphous state having the resistance value higher than the first resistance value;

a third electrode connected to the second electrode and provided on one side of the second phase change thin film;

a fourth electrode provided on the other side of the second phase change thin film; and

a second transistor whose drain terminal is connected to the third electrode, whose source terminal is connected to the fourth electrode, and whose gate terminal is connected to a second word line, wherein

a first memory cell is configured with the first transistor and a first phase change region in the phase change thin film sandwiched between the first electrode and the second electrode,

a second memory cell is configured with the second transistor and a second phase change region in the phase change thin film sandwiched between the third electrode and the fourth electrode,

at a writing operation of information to the first memory cell, the first transistor is turned off and the second transistor is turned on to carry a current from the first electrode to the fourth electrode, and

at a writing operation of information to the second memory cell, the first transistor is turned on and the second transistor is turned off to carry a current from the first electrode to the fourth electrode.