VIRTUAL FUNCTIONAL UNITS FOR VLIW PROCESSORS
A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor “Virtual” views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those types of functional units that are too difficult or too costly to physically duplicate. By providing different virtual views to the different clusters of a VLIW processor, the compiler/scheduler can generate more efficient code for the processor, than a processor without virtual views and the physical unit restricted to a subset of the processor's clusters. The compiler/scheduler guarantees that the restrictions with respect to scheduling of operations for functional units with multiple virtual views is met. NON-clustered processors also benefit from virtual views. By providing multiple virtual views in multiple issue slots of a physical function unit, the compiler/scheduler has more freedom to schedule operations for the functional unit.
1 . A very long instruction word (VLIW) processor system, comprising:
a plurality of issue slots amongst which a VLIW is operated upon in parallel;
a plurality of bypass network clusters for groups of individual ones of the plurality of issue slots so operational results can be passed directly and avoid delays that would otherwise occur through a unified register file;
a plurality of functional processing units in each of the plurality of issue slots with duplicates assigned to each bypass network cluster;
at least two virtual issue slots each disposed in individual ones of the plurality of bypass network clusters; and
a single functional unit connected through the virtual issue slots and appearing in individual ones of the plurality of bypass network clusters;
wherein, the single functional unit is implemented once with multi-porting and can receive operands and output results over the plurality of bypass network clusters to avoid delays that would otherwise occur through said unified register file.
2 . The system of claim 1 , further comprising:
an instruction fetch unit (IFU) for presenting each VLIW to the plurality of issue slots;
a program comprising an number of VLIW instructions for access by the IFU; and
a compiler/scheduler which is aware of the organization and limitations of each issue slot, each bypass network cluster, and the single functional unit connected through the virtual issue slots, and for assembling program instructions accordingly to make optimum use of processor resources.
3 . The system of claim 1 , further comprising:
a load-store unit is included as the single functional unit connected through the virtual issue slots.
4 . A very long instruction word (VLIW) processor, comprising:
a set of eight of issue slots amongst which a VLIW is operated upon in parallel;
a pair of bypass network clusters for two groups of individual ones of the eight issue slots so operational results can be passed directly and avoid delays that would otherwise occur through a unified register file;
a plurality of functional processing units in some of the eight of issue slots with duplicates assigned to each bypass network cluster;
at least two load-store virtual issue slots each disposed in individual ones of the pair of bypass network clusters; and
a single load-store functional unit connected through the virtual issue slots and appearing in individual ones of the plurality of bypass network clusters;
wherein, the single load-store functional unit is implemented once with multi-porting and can receive operands and output results for the two bypass network clusters to avoid delays that would otherwise occur if results had to be passed through said unified register file.
5 . The VLIW processor of claim 4 , further comprising:
an instruction fetch unit (IFU) for presenting each VLIW to the plurality of issue slots; and
a program comprising an number of VLIW instructions for access by the IFU;
wherein, a compiler/scheduler which is aware of the organization and limitations of each issue slot, each bypass network cluster, and the single load-store functional unit connected through the virtual issue slots, is used for assembling program instructions that make optimum use of processor resources.
6 . The VLIW processor of claim 4 , further comprising:
a compiler/scheduler for accommodating any restrictions with respect to scheduling of operations for functional units with multiple virtual views.
7 . A method for reducing construction costs and improving operational performance in a very long instruction word (VLIW) processor, comprising:
grouping issue slots into at least two bypass network clusters; and
virtualizing at least one physical functional unit through multi-porting to appear in at least two bypass network clusters.
8 . A non-clustered statically scheduled VLIW processor providing multiple virtual views of a physical function unit in multiple issue slots, and that provides a compiler/scheduler with increased freedom to schedule operations for the functional unit.
9 . The processor of claim 8 , wherein virtualized functional units, rather than physical duplications of functional units, provide multiple virtual views for some functional units, and such that the virtual views are associated to issue slots and the physical functional unit is shared, and a restriction with respect to mutual exclusive issuing of functional unit operations in the respective issue slots is included in an associated compiler/scheduler.