IP Library Granted Patent US 8,471,172
Granted Patent B2
US 8,471,172 · App. 12/518,599 · Granted Jun 25, 2013

Elimination of short circuits between conductors by laser ablation

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Quick Facts
Patent No.
US 8,471,172
App. No.
12/518,599
Granted
Jun 25, 2013
Kind
B2
Abstract

A method of selectively eliminating electrical shorts and other electrical defects from specific layers of a multilayer electronic device without damaging underlying layers. The method is based on a combination of an automated detection of the defects and selective laser ablation patterning (SLAP).

Claims (24)

1. A method of processing a product defining a plurality of part or whole electronic devices, the method comprising:

patterning a conductive layer by a laser ablation technique to produce a patterned conductive layer;

automated identifying of an electrical defect in the patterned conductive layer by a comparison of the pattern of a plurality of regions of the product; and

the step of eliminating said electrical defect by further application of said laser ablation technique.

2. A method according to claim 1 , wherein the electrical defect is an electrical short, and the step of eliminating said electrical defect comprises removing conductive material so as to isolate one conductive element from another, co-planar conductive element.

3. A method according to claim 2 , wherein the laser ablation is carried out so as to avoid any substantial degradation of a layer directly below the conductive material to be removed.

4. A method according to claim 3 , comprising using a single laser pulse to remove said conductive material and expose the layer directly below the conductive material.

5. A method according to claim 1 , wherein the electrical defect is an electrical short caused by a piece of unwanted conductive material bridging two conductive regions of the plurality of electronic devices.

6. A method according to claim 5 , wherein the two conductive regions are an electrode and an interconnect.

7. A method according to claim 6 , wherein the electrode is a gate electrode and the interconnect is a COM line.

8. A method according to claim 5 , wherein the two conductive regions are the source and drain electrodes of one of said plurality of electronic devices.

9. A method according to claim 5 , wherein the two conductive regions are the pixel electrode of one electronic device and the pixel electrode of another electronic device.

10. A method according to claim 5 , wherein the two conductive regions are a gate electrode and a source and/or drain electrode.

11. A method according to claim 1 , wherein the plurality of electronic devices include one or more organic elements.

12. A method according to claim 5 , comprising laser ablation of a part of at least one of said two conductive regions.

13. A method of processing a product defining a plurality of part or whole electronic devices, the method comprising:

providing a patterned conductive layer defining at least two conductive lines;

automated identifying of an electrical defect caused by a conductive bridge between the said two conductive lines by a comparison of the pattern of a plurality of regions of the product; and

isolating the conductive bridge by removing one or more parts of one of said conductive lines.

14. A method according to claim 13 , wherein isolating the conductive bridge by removing one or more parts of one of said conductive lines is done whilst maintaining a function of said one of said conductive lines.

15. A method of processing a product defining a plurality of part or whole electronic devices, the method comprising:

automated identifying of an electrical defect caused by a conductive bridge between a conductive element at an upper level and a conductive element at a lower level by a comparison of the pattern of a plurality of regions of the product; and

isolating the conductive bridge by removing one or more parts of one of said upper conductive element.

16. A method according to claim 15 , wherein isolating the conductive bridge by removing one or more parts of one of said upper conductive element is done whilst maintaining a function of said upper conductive element.

Assignments (4)
CHANGE OF NAME Recorded May 5, 2016
From: PLASTIC LOGIC LIMITED
To: FLEXENABLE LIMITED
Reel/Frame 038617/0662 →
RELEASE OF SECURITY INTEREST Recorded May 12, 2011
From: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
To: PLASTIC LOGIC LIMITED
Reel/Frame 026271/0377 →
SECURITY AGREEMENT Recorded Aug 3, 2010
From: PLASTIC LOGIC LIMITED
To: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
Reel/Frame 024776/0357 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2009
From: WATTS, JIM; CAIN, PAUL A.; BANACH, MIKE J.
To: PLASTIC LOGIC LIMITED
Reel/Frame 023104/0353 →