Granted Patent B2

US 8,341,301 · App. 12/521,838 · Granted Dec 25, 2012

Abstract

Claims (18)

1. A device having direct memory access (DMA) controller testing capabilities, the device comprises:

a DMA controller, the DMA controller comprises a first data transfer path and a second data transfer path, the first data transfer path and the second data transfer path are mutually independent;

a test unit coupled to the first and second data transfer paths, the test unit is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking, from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data; and

a processor adapted to send to the test unit a test mode indicator and further adapted to send a read command to one data transfer path and a write command to another data transfer path of the DMA controller to be substantially simultaneously executed during the test mode.

2. The device according to claim 1 wherein the device comprises:

a second memory unit that is coupled to first and second data transfer paths, and wherein the transfer of data comprises fetching data from the second memory unit, providing the data to the first data transfer path, sending the data, via the test unit, to the second data transfer path, and sending the data to the second memory unit.

3. A method for testing a direct memory access (DMA) controller, the method comprises:

transferring, by the DMA controller during an operational mode, data between a first memory unit and a second memory unit;

transferring, during a test mode, data between a first data transfer path of the DMA controller and between a second data transfer path of the DMA controller, via a test unit, while masking from the first memory unit at least one control signal associated with the transfer of data; and

sending, a test mode indicator to the DMA controller, and wherein the transferring comprises substantially simultaneously executing a read command by one data transfer path and a write command by another data transfer path of the DMA controller;

wherein the first data transfer path and the second data transfer path are mutually independent.

4. The method according to claim 3 wherein the transferring during the test mode comprises:

fetching data from the second memory unit, providing the data to the first data transfer path, sending the data, via the test unit to the second data transfer path, and sending the data to the second memory unit.

5. The method according to claim 3 wherein the transferring, during a test mode, comprises:

receiving, by a control circuit that belongs to the data unit, a read/write signal, a data transfer request signal and a data transfer size indicator; and in response generating a request acknowledge signal, a data acknowledge signal, an end of data signal and an end of transfer signal.

6. A method for testing a direct memory access (DMA) controller, the method comprises:

transferring, by the DMA controller during an operational mode, first data from a first memory unit to a second memory unit via a first data transfer path of the DMA controller and from the second memory unit to the first memory unit via a second data transfer path of the DMA controller; and

transferring, by the DMA controller during a test mode, second data from first memory unit to a test unit within the DMA controller via the first data transfer path and from the test unit to the first memory unit via the second data transfer path, while masking at least one control signal associated with the transferring of the second data from the second memory unit.

Assignments (33)