HARDWARE TRIGGERED DATA CACHE LINE PRE-ALLOCATION
A computer system includes a data cache supported by a copy-back buffer and pre-allocation request stack. A programmable trigger mechanism inspects each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated. If the store operation memory address occurs within a range defined by START and END programmable registers, then the next cache line that includes a memory address within that defined by a programmable STRIDE register is requested for pre-allocation. Bunches of pre-allocation requests are organized and scheduled by the pre-allocation request stack, and will take their turns to allow the cache lines being replaced to be processed through the copy-back buffer. By the time the processor gets to doing the store operation in the next cache line, such cache line has already been pre-allocated and there will be a cache hit, thus saving stall cycles.
1 . A method for improving processor performance, comprising:
inspecting a memory address of a store operation by a processor to a data cache;
looking for a cache line already allocated within said data cache for said memory address plus a STRIDE value; and
making a pre-allocation request for said cache line if not already pre-allocated;
wherein, said processor is saved from stall cycles caused when there is a cache miss during a store operation to said data cache.
2 . The method of claim 1 , further comprising:
accumulating and scheduling pre-allocation requests with a pre-allocation request stack.
3 . The method of claim 1 , further comprising:
testing whether said memory address of said store operation by said processor to said data cache is included within a range defined by programmable START and END registers, and if so, then allowing said pre-allocation request.
4 . The method of claim 1 , further comprising:
using a copy-back buffer to process cache lines that are being evicted from said data cache.
5 . The method of claim 1 , further comprising:
executing ALLOCATE software commands that will inject pre-allocation requests into said cache line if not already pre-allocated.
6 . A method for improving processor performance, comprising:
inspecting a memory address of a store operation by a processor to a data cache;
looking for a cache line already allocated within said data cache for said memory address plus a STRIDE value;
making a pre-allocation request for said cache line if not already pre-allocated;
accumulating and scheduling pre-allocation requests with a pre-allocation request stack.
testing whether said memory address of said store operation by said processor to said data cache is included within a range defined by programmable START and END registers, and if so, then allowing such pre-allocation request;
using a copy-back buffer to process cache lines that are being evicted from said data cache; and
executing ALLOCATE software commands to inject pre-allocation requests into said pre-allocation request stack;
wherein, said processor is saved from stall cycles caused when there is a cache miss during a store operation to said data cache.
7 . A means for improving processor performance, comprising:
means for inspecting a memory address of a store operation by a processor to a data cache;
means for looking for a cache line already allocated within said data cache for said memory address plus a STRIDE value; and
means for making a pre-allocation request for said cache line if not already pre-allocated;
wherein, said processor is saved from stall cycles caused when there is a cache miss during a store operation to said data cache.
8 . The means of claim 1 , further comprising:
a pre-allocation request stack for accumulating and scheduling pre-allocation requests; and
a copy-back buffer to process cache lines that are being evicted from said data cache.
9 . The method of claim 1 , further comprising:
means for testing whether said memory address of said store operation by said processor to said data cache is included within a range defined by programmable START and END registers, and if so, then allowing said pre-allocation request.
10 . A business method for detecting infringement, comprising:
inspecting a potential infringer's software programs for register equivalents for region_stride, region_start, and region_end, meant to control pre-allocation requests in cache store processor operations.
11 . A business method for detecting infringement, comprising:
inspecting a potential infringer's user manual publications for register equivalents for region_stride, region_start, and region_end, meant to control pre-allocation requests in cache store processor operations.
12 . A computer system, comprising:
a data cache between a processor and a main memory and supported by a copy-back buffer;
a pre-allocation request stack for accumulating and scheduling pre-allocation requests so that each pre-allocation will take its turn waiting for said copy-back buffer to complete its handling of cache lines being replaced in the data cache by pre-allocated cache lines;
a programmable trigger mechanism for inspecting each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated, and if so, for sending a corresponding request to the pre-allocation request stack.
13 . The computer system of claim 12 , further comprising:
programmable registers for holding parameters needed to determine if a next cache line should be pre-allocated.
14 . The computer system of claim 13 , wherein:
the programmable registers are such that if a store operation memory address occurs within a range defined by START and END programmable registers, then the next cache line that includes a memory address within that defined by a programmable STRIDE register will be requested for pre-allocation;
wherein, when the processor does do the store operation in the next cache line, such cache line has already been pre-allocated and there will be a cache hit, thus saving stall cycles.