Granted Patent B2

US 8,067,830 · App. 12/525,265 · Granted Nov 29, 2011

Abstract

Claims (22)

1. A dual or multiple row package comprising an encapsulation around a chip, and a first plurality of terminals and a second plurality of terminals, which first and second plurality of terminals are exposed outside the encapsulation at a first side of the package,

wherein the terminals of the first plurality of terminals are arranged in a first row, wherein a distance between each pair of adjacent terminals in the first row is greater than or equal to a first threshold value;

wherein the terminals of the second plurality of terminals are arranged in a second row, wherein a distance between each pair of adjacent terminals in the second row is greater than or equal to a second threshold; and

wherein a distance between the first row and the second row is smaller than at least the first threshold value.

2. The package as claimed in claim 1 , wherein at least one of the terminals has a substantially rectangular shape and a first length in a first direction which first direction is substantially parallel to the first row and a second length in a second direction which second direction is substantially perpendicular to the first direction, and wherein the first length is smaller than the second length.

3. The package as claimed in claim 1 , wherein the terminals are defined at a stand-off distance from the surface of the encapsulation.

4. The package of claim 1 , wherein each of the terminals is mechanically connected to a contact pad which is mechanically anchored within the encapsulation.

5. The package of claim 4 , wherein at least part of the terminals is connected to a contact pad with a two-dimensional shape differing from the shape of the terminal.

6. The package of claim 5 , wherein the contact pads of the terminals in the outer row are arranged in a circular, oval or octagonal ring, whereas the terminals are arranged along the four edges of the package.

7. The package of claim 1 , wherein at least part of the terminals of the first row are staggered with respect to the terminals of the second row.

8. The package of claim 1 , wherein a die pad with at least one die pad terminal is defined at the first side of the package within the first row.

9. The package of claim 1 , wherein the terminals are defined in a ball grid array layout.

10. The package of claim 4 , wherein the package comprises further features that are mechanically anchored in the encapsulation alike the contact pads, but are defined partially or completely without corresponding terminals.

11. The package of claim 10 , wherein one further feature is an additional pad for use as a wire bonding island.

12. The package of claim 11 , wherein the wire bonding island is a power pad with a size larger than a contact pad and a plurality of wire bonds extend from the island to the chip.

13. The package of claim 12 , wherein the power pad has a terminal in the first row.

14. The package of claim 10 , wherein one further feature is a coil configuration.

15. The package of claim 1 , wherein at least one terminal of the first plurality of terminals is adapted to be used as a test-pad.

16. A dual or multiple row package comprising an encapsulation around a chip, the chip being attached to a die pad, the package having least one contact pad and a first row of terminals, which terminals are exposed outside the encapsulation at a first side of the package, characterized in that the package further comprises test pads that are defined between the first row of terminals and the contact pad.

17. The package of claim 16 , wherein the test pads are provided with terminals, and wherein all terminals have a stand-off from a surface of the encapsulation.

18. The package of claim 1 , wherein the package is soldered to a carrier.

19. The package of claim 16 , wherein test probes are coupled to the test pads.

Assignments (14)