Embedded inductor and method of producing thereof
A method of manufacturing an inductor embedded into a semiconductor chip package ( 100 ) is described, which method comprises providing a carrier ( 102; 202; 302 ) having, between a first side and an opposite second side, a first conductive layer ( 104; 503 ), an intermediate layer ( 205; 505 ), a second conductive layer ( 106; 504 ), forming an inductor and contact pads for the chip by patterning the first conductive layer ( 104; 503 ) from the first side of the carrier ( 102; 202; 302 ), assembling the chip and providing an encapsulation ( 514 ) and forming terminals of the package, by patterning the second conductive layer ( 106; 504 ) from the second side of the carrier.
1. A method of manufacturing an inductor embedded into a semiconductor chip package, which method comprises:
providing a carrier having, between a first side and an opposite second side, a first conductive layer, an intermediate layer, and a second conductive layer,
forming an inductor and contact pads for the chip by patterning the first conductive layer from the first side of the carrier;
assembling a chip to the carrier and providing an encapsulation over the chip, further anchoring the inductor and the contact pads, and
forming terminals of the package which are connected to at least some of the contact pads, by patterning the second conductive layer from the second side of the carrier.
2. The method according to claim 1 , wherein the embedded inductor has a spiral shape.
3. The method as claimed in claim 1 , wherein the embedded inductor is an embedded dipole antenna.
4. The method according to claim 1 , wherein a first coil configuration is defined in an etch mask on top of the first conductive layer, said coil comprising a track with a width such as that during etching of the first conductive layer underlying the etch mask is removed resulting in a freestanding coil configuration.
5. The method as claimed in claim 4 , wherein a further coil configuration is defined in the etch mask and is laterally spaced apart from the first coil configuration.
6. The method as claimed in claim 5 , wherein the further coil configuration comprises a track with a width such that during etching of the first conductive layer the further coil configuration is also defined in the first conductive layer.
7. The method as claimed in claim 1 , wherein a coil configuration is defined in an etch mask on top of the first conductive layer, said coil configuration comprising a track with a width such as that during etching of the first conductive layer the coil configuration is also defined in the first conductive layer.
8. The method as claimed in claim 1 , wherein an embedded coil forms part of a DC-DC converter circuit.
9. The method as claimed in claim 1 , wherein a contact pad is coupled to an end of a coil configuration and connected to a terminal.
10. A semiconductor package having an inductor embedded therein, the package comprising:
a carrier having, between a first side and an opposite second side, a first conductive layer, an intermediate layer, and a second conductive layer;
an inductor and contact pads patterned in the first conductive layer from the first side of the carrier;
a chip assembled in the carrier, the chip and inductor in an encapsulation, the encapsulation anchoring the inductor and contact pads; and
terminals of the package, the terminals connected to at least some of the contact pads, the terminals patterned by the second conductive layer from the second side of the carrier.