Gate drive circuit and display apparatus having the same

1. A gate drive circuit in which stages of the gate drive circuit are connected one after another to each other, the stages outputting gate signals, an m-th stage, ‘m’ being a natural number, comprising:

a pull-up section that outputs a first clock signal as a gate signal of the m-th stage to an output terminal in response to a high voltage of a first node signal which is converted into a high level in accordance with a vertical start signal or a carry signal of one of previous stages of the m-th stage;

a pull-down section that applies a low voltage to the output terminal in response to a high voltage of the gate signal of one of next stages of the m-th stage;

a carry section that outputs the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal;

a first carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal when the gate signal of the m-th stage is maintained at the low voltage;

a second carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to a high voltage of a second clock signal having a different phase from the first clock signal, and

a third carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the gate signal of the one of the next stages of the m-th stage,

wherein a gate of a transistor of the third carry holding section is directly connected to a terminal that provides the gate signal of the one of the next stages of the m-th stage.

2. The gate drive circuit of claim 1 , further comprising a switching section having a second node to which the low voltage is applied when the gate signal of the m-th stage is maintained at the high voltage, and to which the first clock signal is applied when the gate signal of the m-th stage is maintained at the low voltage.

3. The gate drive circuit of claim 2 , further comprising:

a first holding section that applies the low voltage to the output terminal in response to the high voltage of the first clock signal applied to the second node; and

a second holding section that applies the low voltage to the output terminal in response to the high voltage of the second clock signal.

4. The gate drive circuit of claim 3 , wherein:

the pull-up section comprises a first transistor having a gate electrode connected to the first node, a source electrode connected to the output terminal and a drain electrode connected to a first clock terminal that receives the first clock signal,

a fourth holding section comprises a second transistor having a gate electrode connected to the second node, a source electrode connected to a voltage terminal that receives the low voltage and a drain electrode connected to the output terminal,

the carry section comprises a third transistor having a gate electrode connected to the first node, a source electrode connected to a carry terminal that outputs the carry signal of the m-th stage to the one of the next stages of the m-th stage and a drain electrode connected to the first clock terminal, and

the first carry holding section comprises a fourth transistor having a gate electrode connected to the second node, a source electrode connected to the voltage terminal and a drain electrode connected to the carry terminal.

5. The gate drive circuit of claim 4 , wherein a ratio of a channel width of the second transistor to a channel width of the first transistor is substantially the same as a ratio of a channel width of the fourth transistor to a channel width of the third transistor.

6. The gate drive circuit of claim 4 , wherein:

the second holding section comprises a fifth transistor having a gate electrode connected to a second clock terminal that receives the second clock signal, a source connected to the voltage terminal and a drain electrode connected to the output terminal, and

a second carry holding section comprises a sixth transistor having a gate electrode connected to the second clock terminal, a source electrode connected to the voltage terminal and a drain electrode connected to the carry terminal.

7. The gate drive circuit of claim 6 , wherein a ratio of a channel width of the fifth transistor to the channel width of the first transistor is substantially the same as a ratio of a channel width of the sixth transistor to a channel width of the third transistor.

8. The gate drive circuit of claim 4 , wherein:

the pull-down section comprises a seventh transistor having a gate electrode connected to a second input terminal that receives the gate signal of the one of the next stages, a source electrode connected to the voltage terminal and a drain electrode connected to the output terminal, and

the third carry holding section comprises an eighth transistor having a gate electrode connected to the second input terminal, a source electrode connected to the voltage terminal and a drain electrode connected to the carry terminal.

9. The gate drive circuit of claim 8 , wherein a ratio of a channel width of the seventh transistor to a channel width of the first transistor is substantially the same as a ratio of a channel width of the eighth transistor to a channel width of the third transistor.

10. A display apparatus comprising:

a display panel having gate lines and data lines that cross the gate lines, the display panel comprising a display area that displays an image and a peripheral area that surrounds the display area;

a data drive circuit that outputs data signals to the data lines; and

a gate drive circuit in which a plurality of stages are connected one after another to each other, the stages outputting gate signals, an m-th stage, ‘m’ being a natural number, comprising:

a pull-up section that outputs a first clock signal as a gate signal of the m-th stage to an output terminal in response to a high voltage of a first node signal which is converted into a high level in accordance with a vertical start signal or a carry signal of one of previous stages of the m-th stage;

a pull-down section that applies a low voltage to the output terminal in response to a high voltage of the gate signal of one of next stages of the m-th stage;

a carry section that outputs the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal;

a first carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal when the gate signal of the m-th stage is maintained at the low voltage;

a second carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to a high voltage of a second clock signal having a different phase from the first clock signal; and

a third carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the gate signal of the one of the next stages of the m-th stage,

wherein a gate of a transistor of the third carry holding section is directly connected to a terminal that provides the gate signal of the one of the next stages of the m-th stage.

11. The display apparatus of claim 10 , wherein the gate drive circuit is disposed on the peripheral area positioned to a short side direction of the display panel, and the data drive circuit is disposed on the peripheral area positioned to a long side direction of the display panel.

12. The display apparatus of claim 10 , wherein the gate drive circuit is disposed on the peripheral area positioned to a long side direction of the display panel, and the data drive circuit is disposed on the peripheral area positioned to a short side direction of the display panel.

13. The display apparatus of claim 10 , wherein the gate drive circuit further comprises a switching section having a second node to which the low voltage is applied when the gate signal of the m-th stage is maintained at the high voltage, and to which the first clock signal is applied when the gate signal of the m-th stage is maintained at the low voltage.

14. The display apparatus of claim 13 , wherein the gate drive circuit further comprises:

a first holding section that applies the low voltage to the output terminal in response to the high voltage of the first clock signal applied to the second node; and

a second holding section that applies the low voltage to the output terminal in response to the high voltage of the second clock signal.

15. The display apparatus of claim 14 , wherein:

the pull-up section comprises a first transistor having a gate electrode connected to the first node, a source electrode connected to the output terminal and a drain electrode connected to a first clock terminal that receives the first clock signal,

a fourth holding section comprises a second transistor having a gate electrode connected to the second node, a source electrode connected to a voltage terminal that receives the low voltage and a drain electrode connected to the output terminal,

the carry section comprises a third transistor having a gate electrode connected to the first node, a source electrode connected to a carry terminal that outputs the carry signal of the m-th stage to the one of the next stages of the m-th stage and a drain electrode connected to the first clock terminal, and

the first carry holding section comprises a fourth transistor having a gate electrode connected to the second node, a source electrode connected to the voltage terminal and a drain electrode connected to the carry terminal.

16. A first stage, in a gate drive circuit for driving a display panel, for reducing ripple generation between the first stage and a next stage, the first stage comprising:

a pull-up section that outputs a first clock signal as a gate signal of the m-th stage to an output terminal in response to a high voltage of a first node signal which is converted into a high level in accordance with a vertical start signal or a carry signal of one of previous stages of the m-th stage, the pull-up section being a transistor having a pull-up section channel width;

a pull-down section that applies a low voltage to the output terminal in response to a high voltage of the gate signal of one of next stages of the m-th stage, the pull-down section being a transistor having a pull-down section channel width;

a carry section that outputs the first clock signal as a carry signal of the math stage in response to the high voltage of the first node signal, the carry section being a transistor having a carry section channel width;

a first carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal when the gate signal of the m-th stage is maintained at the low voltage;

a second carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to a high voltage of a second clock signal having a different phase from the first clock signal;

a third carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the gate signal of the one of the next stages of the m-th stage, the third carry holding section being a transistor having a third carry holding section channel width;

wherein a ratio of the third carry holding section channel width to the carry section channel width is substantially the same as a ratio of the pull-down section channel width to the pull-up section channel width, and

wherein a gate of a transistor of the third carry holding section is directly connected to a terminal that provides the gate signal of the one of the next stages of the m-th stage.