Soft start sequencer for starting multiple voltage regulators
View Patent ↗A soft start sequencer is disclosed for starting a plurality of voltage regulators, the soft start sequencer comprising a first clock for clocking a plurality of soft start circuits, wherein each soft start circuit for ramping a reference signal from a first value to a second value over a ramp time after a delay time. Each soft start circuit comprises a divider operable to divide the first clock by an integer N to generate a second clock, a first counter clocked by the first clock, the first counter operable to time the delay time, and a second counter clocked by the second clock, the second counter operable to time the ramp time after the delay time.
1. A soft start sequencer for starting a plurality of voltage regulators, the soft start sequencer comprising a first clock for clocking a plurality of soft start circuits, wherein each soft start circuit is for ramping a reference signal from a first value to a second value over a ramp time after a delay time, each soft start circuit comprising:
a divider operable to divide the first clock by an integer N to generate a second clock;
a first counter clocked by the first clock, the first counter operable to time the delay time; and
a second counter clocked by the second clock, the second counter operable to time the ramp time after the delay time.
2. The soft start sequencer as recited in claim 1 , wherein:
a first one of the voltage regulators generates a first output voltage level in response to a first reference signal generated by a first one of the soft start circuits; and
a second one of the voltage regulators generates a second output voltage level in response to a second reference signal generated by a second one of the soft start circuits.
3. The soft start sequencer as recited in claim 2 , wherein the first output voltage level is different from the second output voltage level.
4. The soft start sequencer as recited in claim 1 , wherein the first counter comprises a down counter and the second counter comprises an up counter.
5. The soft start sequencer as recited in claim 1 , wherein the reference signal generated by each soft start circuit comprises one of a reference voltage and reference current.
6. The soft start sequencer as recited in claim 1 , wherein each soft start circuit further comprises a digital-to-analog converter for converting an output of the second counter into the reference signal.
7. The soft start sequencer as recited in claim 1 , wherein the first counters of the soft start circuits are started together by a start signal.
8. The soft start sequencer as recited in claim 1 , further comprising a non-volatile memory for storing the integer N for each of the dividers and for storing a delay value for each of the first counters.
9. A method of starting a plurality of voltage regulators, the method comprising:
clocking a plurality of soft start circuits with a first clock, each soft start circuit ramping a reference signal from a first value to a second value over a ramp time after a delay time;
dividing the first clock by an integer N to generate a second clock;
clocking a first counter with the first clock, the first counter operable to time the delay time; and
clocking a second counter with the second clock, the second counter operable to time the ramp time after the delay time.
10. The method as recited in claim 9 , wherein:
a first one of the voltage regulators generates a first output voltage level in response to a first reference signal generated by a first one of the soft start circuits; and
a second one of the voltage regulators generates a second output voltage level in response to a second reference signal generated by a second one of the soft start circuits.
11. The method as recited in claim 10 , wherein the first output voltage level is different from the second output voltage level.
12. The method as recited in claim 9 , wherein the first counter comprises a down counter and the second counter comprises an up counter.
13. The method as recited in claim 9 , wherein the reference signal generated by each soft start circuit comprises one of a reference voltage and reference current.
14. The method as recited in claim 9 , wherein each soft start circuit further comprises a digital-to-analog converter for converting an output of the second counter into the reference signal.
15. The method as recited in claim 9 , further comprising starting the first counters of the soft start circuits together by a start signal.
16. The method as recited in claim 9 , further comprising storing the integer N for each of the dividers and storing a delay value for each of the first counters in a non-volatile memory.
17. A data storage device comprising:
a storage medium; and
control circuitry operable to write data to the storage medium and read data from the storage medium, the control circuitry comprising a plurality of voltage regulators and a soft start sequencer for starting the plurality of voltage regulators, the soft start sequencer comprising a first clock for clocking a plurality of soft start circuits, wherein each soft start circuit is for ramping a reference signal from a first value to a second value over a ramp time after a delay time, each soft start circuit comprising:
a divider operable to divide the first clock by an integer N to generate a second clock;
a first counter clocked by the first clock, the first counter operable to time the delay time; and
a second counter clocked by the second clock, the second counter operable to time the ramp time after the delay time.
18. The data storage device as recited in claim 17 , wherein the storage medium comprises a disk of a disk drive, the disk drive comprising a head actuated over the disk.
19. The data storage device as recited in claim 17 , wherein the storage medium comprises a plurality of non-volatile memories of a solid state drive.