Regulator having phase compensation circuit
View Patent ↗A regulator circuit includes an output transistor that generates an output current in accordance with a control voltage that is applied to a control terminal of the output transistor. A differential amplifier provides feedback control of the control voltage in accordance with a level of the output current. A phase compensation circuit is connected to the differential amplifier and the control terminal of the output transistor. The phase compensation circuit adjusts an output impedance of the differential amplifier. The phase compensation circuit includes a variable resistor that decreases the output impedance of the differential amplifier when the output current increases.
1. A regulator, comprising:
an output transistor including a control terminal to which a control voltage is applied, wherein the output transistor generates an output current in accordance with the control voltage;
a differential amplifier that controls via feedback the control voltage in accordance with a level of the output current; and
a phase compensation circuit connected between the differential amplifier and the control terminal of the output transistor, wherein the phase compensation circuit adjusts an output impedance of the differential amplifier, and wherein the phase compensation circuit includes a variable resistor that decreases the output impedance of the differential amplifier when the output current increases.
2. The regulator of claim 1 , wherein the variable resistor includes a transistor driven with an amplification signal output from the differential amplifier in accordance with the level of the output current.
3. The regulator of claim 1 , wherein:
the differential amplifier detects the output current and generates an inverted amplification signal and a non-inverted amplification signal; and
the variable resistor includes a first transistor having a first current terminal to which a first voltage corresponding to the non-inverted amplification signal is applied, a second current terminal to which a second voltage corresponding to the inverted amplification signal is applied, and a control terminal to which the control voltage corresponding to the non-inverted amplification signal is applied.
4. The regulator of claim 3 , wherein the phase compensation circuit includes:
a first cascode circuit including cascode-connected second and third transistors, wherein the first cascode circuit generates the first voltage at a first connection node between the second and third transistors based on the non-inverted amplification signal; and
a second cascode circuit including cascode-connected fourth and fifth transistors, wherein the second cascode circuit generates the second voltage at a second connection node between the fourth and fifth transistors based on the inverted amplification signal;
wherein the first transistor is connected between the first and second connection nodes.
5. The regulator of claim 1 , further comprising:
a buffer circuit connected between the phase compensation circuit and the control terminal of the output terminal, wherein the buffer circuit generates the control voltage.
6. The regulator of claim 5 , wherein the variable resistor has a resistance value controlled by the control voltage.
7. The regulator of claim 1 , wherein the regulator is a low dropout regulator.
8. A regulator comprising:
an output transistor that generates an output current in accordance with a control voltage based on an input voltage;
a differential amplifier that detects the output current and includes a first output terminal for providing a non-inverted amplification signal that controls the control voltage, and a second output terminal for providing an inverted amplification signal that is complementary to the non-inverted amplification signal;
a phase compensation circuit that controls a loop gain of the regulator, wherein the phase compensation circuit includes:
a first transistor having first and second current terminals and being responsive to the non-inverted amplification signal;
a second transistor driven by the inverted amplification signal and having a first current terminal to which the input voltage is applied, and a second terminal that is connected to the first current terminal of the first transistor;
a third transistor driven by a bias voltage and having a first current terminal that is connected to the second current terminal of the second transistor, and a second current terminal that is connected to the first output terminal of the differential amplifier; and
a fourth transistor driven by the inverted amplification signal and having a first current terminal to which the input voltage is applied, and a second terminal that is connected to the second current terminal of the first transistor.
9. The regulator of claim 8 , wherein the output transistor and the first transistor are driven by the same control voltage that is in accordance with the non-inverted amplification signal.
10. The regulator of claim 9 , further comprising a buffer circuit connected to the differential amplifier, wherein the buffer circuit generates the control voltage from the non-inverted amplification signal.