IP Library Granted Patent US 7,986,616
Granted Patent B2
US 7,986,616 · App. 12/535,739 · Granted Jul 26, 2011

System and method for maintaining a layer 2 modification buffer

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Quick Facts
Patent No.
US 7,986,616
App. No.
12/535,739
Granted
Jul 26, 2011
Kind
B2
Abstract

A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Claims (23)

1. A network device comprising:

ports for sending and receiving data;

a layer 2 table;

a modification buffer; and

an ingress module that includes a first buffer and FIFO buffer, the ingress module being configured for performing lookups for layer 2 switching and for maintaining the layer 2 table and the modification buffer,

wherein the ingress module is configured to add entries to the modification buffer when the layer 2 table is modified and in an order in which the layer 2 table was modified, such that the layer 2 table can be reconstructed based on the entries of the modification buffer,

wherein the ingress module is configured to perform a learn operation, the learn operation including marking a packet for a learn operation and storing a learn entry associated with a packet in the first buffer, wherein the first buffer includes an entry for each port on the network device and each entry includes a first bit for indicating a status of the packet and a second bit for indicating if there is a source address in the entry, and wherein if the status of the packet is known, if the packet is received without errors, and if there is room in the FIFO buffer, the learn entry is copied from the first buffer to the FIFO buffer.

2. The network device of claim 1 , wherein the FIFO buffer is configured as a simple queue, wherein an entry at the head of the queue competes with other instructions to enter an ingress pipeline.

3. The network device of claim 1 , wherein the first buffer comprises a plurality of entries for storing information and wherein the ingress module is configured to look up entries in the first buffer such that a slot in the first buffer associated with the second bit is available for a new learn instruction when the second bit associated with the slot is clear and the source address in the slot is cleared.

4. The network device of claim 1 , wherein the ingress module is configured to implement a round-robin arbitration scheme to determine which entry in the first buffer should be transmitted to the FIFO buffer.

5. The network device of claim 1 , wherein the modification buffer comprises a 16 entry table and a counter is used at the beginning of an ingress pipeline to block instructions that would update the modification buffer and cause the modification buffer to overflow.

6. The network device of claim 1 , wherein the ingress module is further configured to set a lock bit when entries are read out of the modification buffer, wherein the lock bit prevents new operations that can affect the modification buffer from entering an ingress pipeline.

7. The network device of claim 6 , wherein the ingress module is further configured to clear the lock bit after entries are read out the modification buffer and to initialize a write pointer to point to the first entry of the modification buffer.

8. The network device of claim 1 , wherein the ingress module is configured to perform one of dynamic enablement or disablement of layer 2 operations by a mode bit, wherein when operations are disabled, no operations are added to the modification buffer.

9. A method for processing packets in a network device, the method comprising:

performing lookup operations for layer 2 switching;

maintaining a layer 2 table;

recording operations performed on the layer 2 table in a modification buffer when the layer 2 table is updated, wherein entries are added to the modification buffer in an order in which the layer 2 table is modified, such that the layer 2 table can be reconstructed based on the entries of the modification buffer;

scheduling a learn instruction by marking a packet for a learn operation, storing a learn entry associated with the packet in a first buffer, wherein the first buffer includes an entry for each port on the network device and each entry includes a first bit for indicating a status of the packet and a second bit for indicating if there is a source address in the entry, and wherein if the status of the packet is known, if the packet is received without errors, and if there is room in a FIFO buffer, copying the learn entry from the first buffer to the FIFO buffer; and

wherein the ingress module is configured to perform a learn operation, the learn operation including marking a packet for a learn operation and storing a learn entry associated with a packet in the first buffer, the learn entry is copied from the first buffer to the FIFO buffer.

10. The method of 9 , further comprising blocking instructions that will update the modification buffer and cause the modification buffer to overflow when a counter at the beginning of an ingress pipeline is equal to a predefined value.

11. The method of 9 , further comprising setting a lock bit when entries are read out of the modification buffer, wherein the lock bit prevents new operations that can affect the modification buffer from entering an ingress pipeline, clearing the lock bit after entries are read out of the modification buffer and initializing a write pointer to point to the first entry of the modification buffer.

12. The method of 9 , further comprising dynamically disabling layer 2 operations by a mode bit, wherein no operations are added to the modification buffer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →