Method for Shifting Data Bits Multiple Times Per Clock Cycle
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.
1 . A method, comprising:
receiving first and second sets of data bits at a shifting device;
controlling, during each clock cycle, rotation of data bits in the first data set and subsequently data bits in the second data set in the shifting device based on a phase control signal to form first and second controlled data sets;
interleaving the first and second controlled data sets in the shifting device to form first and second interleaved data sets;
selecting one of the first and second interleaved data sets in a selector based on a portion of the phase control signal during a second half of the clock cycle; and
transmitting the selected data set from the selector.
2 . The method of claim 1 , wherein the phase control signal comprises:
a parity signal that keeps track of parity of data bit position of the data bits in the selected data set;
a hold signal that holds rotation or allows rotation;
a direction signal that controls a direction of rotation; and
a shift size signal that determines a shift size during the rotation of the first data set and the second data set.
3 . The method of claim 1 , wherein the selecting comprises:
performing an exclusive OR operation on the parity and the direction signals in a selector controller to produce a result signal; and
using the result signal to perform the selecting.
4 . The method of claim 1 , wherein the interleaving comprises:
forming the first interleaved data set through interleaving even-numbered ones of the data bits from the first controlled data set and odd-numbered ones of the data bits from the second controlled data set; and
forming the second interleaved data set through interleaving odd-numbered ones of the data bits from the first controlled data set with even-numbered ones of the data bits from the second controlled data set.
5 . The method of claim 1 , wherein the controlling comprises:
determining whether the first and second data sets are aligned with the clock cycle;
wherein when the first and second data sets are misaligned with the clock signal, the controlling further comprises,
determining a direction of the misalignment;
shifting the data bits in the first data set by one bit in the direction of the misalignment during a first half of the clock cycle, and
shifting the data bits in the second data set by one bit in the direction of the misalignment during a second half of the clock cycle.
6 . The method of claim 1 , wherein the interleaving comprises:
delaying the first and second interleaved data sets;
receiving a selection control signal based on the portion of the phase control signal; and
performing the selecting.
7 . The method of claim 1 , wherein the controlling comprises:
determining whether the first and second data sets are aligned with the clock cycle;
wherein when the first and second data sets are misaligned with the clock signal, the controlling further comprises,
determining a direction of the misalignment;
shifting the data bits in the first data set by one bit in the direction of the misalignment during one of a rising or falling edge of the clock cycle, and
shifting the data bits in the second data set by one bit in the direction of the misalignment during another one of the rising edge or falling edge of the clock cycle.
8 . The method of claim 1 , wherein the controlling comprises:
copying the shifted data bits of the first data set to form the second data set.
9 . The method of claim 1 , wherein the controlling comprises:
assigning critical bits to be ones of the data bits at a data bit value transition point in the first and second data sets; and
performing the rotating of the data bits using the critical bits.