Storage devices with soft processing

1. A storage system comprising:

a first section having:

a storage array including a plurality of storage elements, each storage element operable to be written to one of a discrete set of N physical states;

a read circuit for selecting one or more storage elements and generating, for each selected storage element, an analog signal representative of the physical state of the selected storage element; and

a modulation circuit for accepting the analog signal to form a modulated representation of the analog signal from the read circuit capable of representing greater than N different states; and

a second section interfacing the first section having:

a demodulation circuit for accepting the modulated representation of the analog signal from the modulation circuit to recover the analog signal; and

a signal processing circuit for processing the recovered analog signal to generate a plurality of outputs, each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

2. The storage system of claim 1 , wherein the modulation circuit is configured to form a discrete-state representation of the analog signal from the read circuit, wherein the discrete-state representation is capable of representing greater than N different states.

3. The storage system of claim 1 , wherein the modulation circuit includes an analog-to-digital converter (ADC).

4. The storage system of claim 2 , wherein the demodulation circuit includes a digital-to-analog converter (DAC).

5. The storage system of claim 2 , wherein the ADC includes a linear ADC component.

6. The storage system of claim 2 , wherein the ADC includes a non-linear ADC component.

7. The storage system of claim 1 , wherein the modulated representation of the analog signal from the read circuit includes a signal of multiple quantization levels.

8. The storage system of claim 7 , wherein the signal of multiple quantization levels is transmitted via a serial line to the demodulation circuit.

9. The storage system of claim 7 , wherein the signal of multiple quantization levels is transmitted via multiple parallel lines to the demodulation circuit.

10. The storage system of claim 1 , wherein the modulation circuit is further configured for applying a signal modulation technique to the analog signal from the read circuit to form the modulated representation of the analog signal.

11. The storage system of claim 10 , wherein the signal modulation technique includes pulse-code modulation.

12. The storage system of claim 10 , wherein the signal modulation technique includes pulse width modulation.

13. The storage system of claim 10 , wherein the signal modulation technique includes pulse amplitude modulation.

14. The storage system of claim 10 , wherein the signal modulation technique includes quadrature amplitude modulation.

15. The storage system of claim 10 , wherein the signal modulation technique includes phase modulation.

16. The storage system of claim 10 , wherein the signal modulation technique includes pulse-position modulation.

17. The storage system of claim 10 , wherein the signal modulation technique includes stochastic modulation, and the modulated representation of the analog signal is provided as a random binary sequence of a specified probabilistic distribution.

18. The storage system of claim 1 , wherein the first section is implemented as a first integrated circuit, and the second section is implemented as a second integrated circuit.

19. The storage system of claim 18 , further comprising a communication link between the first and the second integrated circuits.