Semiconductor memory device of open bit line type

1. A semiconductor memory device comprising:

a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell;

a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and

an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.

2. The semiconductor memory device as claimed in claim 1 , wherein the dummy word lines in the memory mats adjacent to both sides of the selected memory mat are respectively activated when memory mats other than the memory mats positioned at both ends are selected from the memory mats.

3. The semiconductor memory device as claimed in claim 1 , wherein among the memory mats, the memory mats positioned at both ends are simultaneously selected, and the dummy word lines in the memory mats adjacent to the memory mats positioned at the both ends are respectively activated.

4. The semiconductor memory device as claimed in claim 1 , wherein

the memory mats include a first memory mat positioned at one end, a second memory mat adjacent to the first memory mat, a third memory mat positioned at the other end, and a fourth memory mat adjacent to the third memory mat,

the first memory mat and the third memory mat are simultaneously selected, and

when the first and third memory mats are selected, the activating unit activates both of the dummy word lines belonging to the second and fourth memory mats, when the second memory mat is selected, the activating unit activates the dummy word line belonging to the first memory mat without activating the dummy word line belonging to the third memory mat, and when the fourth memory mat is selected, the activating unit activates the dummy word line belonging to the third memory mat without activating the dummy word line belonging to the first memory mat.

5. The semiconductor memory device as claimed in claim 1 , wherein the dummy word lines are located at an interval of every two of the word lines.

6. The semiconductor memory device as claimed in claim 5 , wherein within the memory mats, a plurality of active region arrays aligned along a wiring direction of the word lines are arranged, and the dummy word lines are wired along an element isolation region located between adjacent active region arrays.

7. The semiconductor memory device as claimed in claim 1 , wherein the memory mats further include an unused word line connected to a dummy cell, and the unused word line is fixed in an inactive state.

8. A semiconductor memory device comprising:

a plurality of memory mats each including a plurality of word lines, a plurality of dummy word lines located at an interval of every two of the word lines, a plurality of bit lines intersecting each of the word line and each of the dummy word line, and a plurality of memory cells each located at an intersection of each of the word line and each of the bit line;

a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and

an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat, wherein

within the memory mats, a plurality of active region arrays aligned along a wiring direction of the word lines are arranged, and the dummy word lines are wired along an element isolation region located between the adjacent active region arrays.

9. The semiconductor memory device as claimed in claim 8 , wherein the memory cell is located at each intersection of two of the adjacent bit lines and two of the adjacent word lines.

10. The semiconductor memory device as claimed in claim 8 , wherein the bit lines are alternately connected to the sense amplifier arrays located on one adjacent side and the sense amplifier arrays located on the other adjacent side.