Electrostatic discharge clamp circuit
An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.
1. An electrostatic discharge (ESD) clamp circuit, comprising:
a first resistor, having a first end coupled to a first rail;
a second resistor, having a second end coupled to a second rail;
a first transistor, wherein a control end of the first transistor is coupled to a first end of the second resistor, and a second end of the first transistor is coupled to the second rail;
a first diode unit, having two ends coupled to a second end of the first resistor and a first end of the first transistor respectively;
a second transistor, wherein a control end of the second transistor is coupled to the second end of the first resistor, a first end of the second transistor is coupled to the first rail, and a second end of the second transistor is coupled to the first end of the second resistor; and
a third transistor, wherein a control end of the third transistor is coupled to the first end of the second resistor, a first end of the third transistor is coupled to the first rail, and a second end of the third transistor is coupled to the second rail.
2. The ESD clamp circuit according to claim 1 , wherein the first transistor is an N-channel metal oxide semiconductor (NMOS) transistor, the second transistor is a P-channel metal oxide semiconductor (PMOS) transistor, and the third transistor is an NMOS transistor.
3. The ESD clamp circuit according to claim 1 , wherein the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, and the third transistor is a PMOS transistor.
4. The ESD clamp circuit according to claim 1 , wherein the third transistor is a big field effect transistor (BIGFET).
5. The ESD clamp circuit according to claim 1 , further comprising:
a fourth transistor, wherein a control end of the fourth transistor is coupled to the second end of the first resistor, a first end of the fourth transistor is coupled to the first rail, and a second end of the fourth transistor is coupled to the second rail.
6. The ESD clamp circuit according to claim 5 , wherein the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor.
7. The ESD clamp circuit according to claim 5 , wherein the third transistor and the fourth transistor are BIGFETs.
8. The ESD clamp circuit according to claim 5 , further comprising:
a second diode unit, coupled between the second end of the second transistor and the first end of the second resistor.
9. The ESD clamp circuit according to claim 8 , wherein the second diode unit comprises a second diode string formed by a plurality of diodes connected in series, and two ends of the second diode string are coupled to the second end of the second transistor and the first end of the second resistor respectively.
10. The ESD clamp circuit according to claim 9 , wherein the diodes are implemented by transistors.
11. The ESD clamp circuit according to claim 1 , wherein the first diode unit comprises a first diode string formed by a plurality of diodes connected in series, and two ends of the first diode string are coupled to the first end of the first transistor and the second end of the first resistor respectively.
12. The ESD clamp circuit according to claim 11 , wherein the diodes are implemented by transistors.
13. The ESD clamp circuit according to claim 1 , further comprising:
a second diode unit, coupled between the second end of the second transistor and the first end of the second resistor.
14. The ESD clamp circuit according to claim 13 , wherein the second diode unit comprises a second diode string formed by a plurality of diodes connected in series, and two ends of the second diode string are coupled to the second end of the second transistor and the first end of the second resistor respectively.
15. The ESD clamp circuit according to claim 14 , wherein the diodes are implemented by transistors.
16. The ESD clamp circuit according to claim 1 , wherein the first rail and the second rail are power rails.
17. An electrostatic discharge (ESD) clamp circuit, comprising:
a first resistor, having a first end coupled to a first rail;
a second resistor, having a second end coupled to a second rail;
a first transistor, wherein a control end of the first transistor is coupled to a first end of the second resistor, a first end of the first transistor is coupled to a second end of the first resistor, and a second end of the first transistor is coupled to the second rail;
a second transistor, wherein a control end of the second transistor is coupled to the second end of the first resistor, and a first end of the second transistor is coupled to the first rail; and
a second diode unit, having two ends coupled to the first end of the second resistor and a second end of the second transistor respectively;
a third transistor, wherein a control end of the third transistor is coupled to the first end of the second resistor, a first end of the third transistor is coupled to the first rail, and a second end of the third transistor is coupled to the second rail.
18. The ESD clamp circuit according to claim 17 , wherein the first transistor is an N-channel metal oxide semiconductor (NMOS) transistor, the second transistor is a P-channel metal oxide semiconductor (PMOS) transistor, and the third transistor is an NMOS transistor.
19. The ESD clamp circuit according to claim 17 , wherein the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, and the third transistor is a PMOS transistor.
20. The ESD clamp circuit according to claim 17 , wherein the third transistor is a big field effect transistor (BIGFET).
21. The ESD clamp circuit according to claim 17 , further comprising:
a fourth transistor, wherein a control end of the fourth transistor is coupled to the second end of the first resistor, a first end of the fourth transistor is coupled to the first rail, and a second end of the fourth transistor is coupled to the second rail.
22. The ESD clamp circuit according to claim 21 , wherein the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor.
23. The ESD clamp circuit according to claim 21 , wherein the third transistor and the fourth transistor are BIGFETs.
24. The ESD clamp circuit according to claim 21 , further comprising:
a first diode unit, having two ends coupled to the second end of the first resistor and the first end of the first transistor respectively.
25. The ESD clamp circuit according to claim 24 , wherein the first diode unit comprises a first diode string formed by a plurality of diodes connected in series, and two ends of the first diode string are coupled to the first end of the first transistor and the second end of the first resistor respectively.
26. The ESD clamp circuit according to claim 25 , wherein the diodes are implemented by transistors.
27. The ESD clamp circuit according to claim 17 , further comprising:
a first diode unit, coupled between the second end of the first resistor and the first end of the first transistor.
28. The ESD clamp circuit according to claim 27 , wherein the first diode unit comprises a first diode string formed by a plurality of diodes connected in series, and two ends of the first diode string are coupled to the first end of the first transistor and the second end of the first resistor respectively.
29. The ESD clamp circuit according to claim 28 , wherein the diodes are implemented by transistors.
30. The ESD clamp circuit according to claim 17 , wherein the second diode unit comprises a second diode string formed by a plurality of diodes connected in series, and two ends of the second diode string are coupled to the second end of the second transistor and the first end of the second resistor respectively.
31. The ESD clamp circuit according to claim 30 , wherein the diodes are implemented by transistors.
32. The ESD clamp circuit according to claim 17 , wherein the first rail and the second rail are power rails.