Configurable clock signal generator
View Patent ↗A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.
1. A system to provide a low-power clock signal or a low-noise clock signal, comprising:
a low-dropout voltage regulator (LDO);
a low-power bandgap voltage reference generator coupled to the LDO and configured to provide a low-power voltage reference to the LDO;
a low-noise bandgap voltage reference generator coupled to the LDO and configured to provide a low-noise voltage reference to the LDO;
a switch configured to switch a voltage reference input of the LDO to the low-noise bandgap voltage reference or to the low-power bandgap voltage reference; and
a crystal oscillator coupled to the LDO and configured to provide a low-power clock signal or a low-noise clock signal based on whether a low-noise voltage reference or a low-power voltage reference is selected as a voltage reference input to the LDO.
2. The system of claim 1 , further comprising:
a control unit configured to provide a control signal to switch the voltage reference input of the LDO to the low-noise bandgap voltage reference for low-noise mode of operation and to switch the voltage reference input of the LDO to the low-power bandgap voltage reference for low-power mode of operation.
3. The system of claim 2 , wherein the control unit generates a signal to power down the low-noise bandgap voltage reference generator upon switching the voltage reference input of the LDO to the low-power bandgap voltage reference and to power down the low-power bandgap voltage reference generator upon switching the voltage reference input of the LDO to the low-noise bandgap voltage reference.
4. The system of claim 1 , wherein a bandgap noise current of the low-power bandgap voltage reference generator is smaller than a bandgap noise current of the low-noise bandgap voltage reference generator.
5. The system of claim 1 , wherein an emitter resistance of the low-noise bandgap voltage reference generator is smaller than an emitter resistance of the low-power bandgap voltage reference generator.
6. The system of claim 1 , wherein transistor sizes of the low-noise bandgap voltage reference generator are greater than transistor sizes of the low-power bandgap voltage reference generator.
7. A system to provide a low-power or a low-noise clock signal, comprising:
a crystal oscillator configured to provide an input clock signal;
a low-power limiter configured to receive the input clock signal and configured to limit the input clock signal and generate a low-power output clock signal;
a low-noise limiter coupled to the crystal oscillator and configured to limit the input clock signal and generate a low-noise output clock signal; and
a switch coupled to the low-power output clock signal and the low-noise output clock signal and configured to select either the low-noise output clock signal or the low-power output clock signal to be an output clock signal.
8. The system of claim 7 , further comprising:
a control unit configured to provide a control signal to the switch to select the low-noise output clock signal for low-noise mode of operation and to select the low-power output clock signal for low-power mode of operation.
9. The system of claim 8 , wherein the control unit is configured to generate a signal to power down the low-noise limiter if the low-power output clock signal is selected and to power down the low-power limiter if the low-noise output clock signal is selected.
10. The system of claim 7 , wherein the low-power limiter is configured to limit the clock signal input using a low bias current resulting in the low-power output clock signal.
11. The system of claim 7 , wherein the low-noise limiter is configured to limit the clock signal input using a high bias current resulting in a low-noise output clock signal.
12. The system of claim 7 , wherein a bias current of the low-power limiter is smaller than a bias current of the low-noise limiter.
13. The system of claim 7 , wherein a size of transistors of the low-power limiter is smaller than a size of transistors of the low-noise limiter.
14. The system of claim 7 , wherein the switch is a mux.
15. A system to provide a clock signal, comprising:
a low-dropout voltage regulator (LDO);
a low-power bandgap voltage reference generator coupled to the low-dropout regulator and configured to provide a low-power voltage reference to the LDO;
a low-noise bandgap voltage reference coupled to the low-dropout regulator and configured to provide a low-noise voltage reference to the LDO;
a first switch configured to switch a voltage reference input of the LDO to the low-noise bandgap voltage reference or to the low-power bandgap voltage reference;
a crystal oscillator coupled to the LDO and configured to provide an input clock signal;
a low-power limiter circuit coupled to the input clock signal and configured to generate a low-power output clock signal;
a low-noise limiter circuit coupled to the input clock signal and configured to generate a low-noise output clock signal; and
a second switch configured to select the low-noise output clock signal or the low-power output clock signal.
16. The system of claim 15 , further comprising:
at least one control unit configured to provide a control signal to switch the voltage reference input of the LDO to the low-noise bandgap voltage reference and select the low-noise output clock signal for low-noise mode of operation and to switch the voltage reference input of the LDO to the low-power bandgap voltage reference and select the low-power output clock signal for low-power mode of operation.
17. A method to provide a low-power clock signal or a low-noise clock signal, comprising:
determining whether a low-power mode of operation or a low-noise mode of operation is in use;
switching a voltage reference input of a low-dropout voltage regulator (LDO) to a low-power voltage reference or to a low-noise voltage reference;
providing a constant voltage output using the LDO to a crystal oscillator;
generating an input clock signal using the crystal oscillator;
limiting the input clock signal using a low-power limiter to generate a low-power output clock signal or limiting the clock signal using a low-noise limiter to generate a low-noise output clock signal; and
selecting the low-power output clock signal or the low-noise output clock signal.
18. The method of claim 17 , further comprising:
powering down the low-power bandgap voltage reference generator and the low-power limiter upon switching to the low-noise voltage reference and upon selecting the low-noise output clock signal; and
powering down the low-noise bandgap voltage reference generator and the low-noise limiter upon switching to the low-power voltage reference and upon selecting the low-power output clock signal.
19. A non-transitory tangible computer-readable medium having stored thereon, computer-executable instructions that, if executed by a computing device, cause the computing device to:
determine whether a low-power mode of operation or a low-noise mode of operation is in use;
generate a first control signal to switch a voltage reference input of a low-dropout voltage regulator (LDO) to a low-power voltage reference or to a low-noise voltage reference based on whether said low-power mode of operation or said low-noise mode of operation is in use; and
generate a second control signal to select a low-power output clock signal from a low-power limiter or a low-noise output clock signal from a low-noise limiter based on whether said low-power mode of operation or said low-noise mode of operation is in use.
20. The non-transitory tangible computer-readable medium of claim 19 , further comprising computer-executable instructions that, if executed by a computing device, cause the computing device to:
generate a third control signal to power-down the low-power bandgap voltage reference generator and a fourth control signal to power-down a low-power limiter upon selecting the low-noise voltage reference and the low-noise output clock signal; and
generate a fifth control signal to power-down the low-noise bandgap voltage reference generator and a sixth control signal to power-down a low-noise limiter upon selecting the low-power voltage reference and the low-power output clock signal.