High power and high frequency gallium nitride based digital to analog converter for direct digital radio frequency power waveform synthesis

1. A high power digital to analog converter comprising

an array of n transistors arranged in a binary sequence, in which any transistor in the sequence is twice as large as its preceding transistor,

the array of n transistors including respective collector terminals tied together,

a depletion mode field-effect transistor (FET) including a source terminal connected to the respective collector terminals, and a drain terminal for providing a drain current, and

an array of n switches for selectively activating the n transistors of the array, and selectively providing binary weighted collector currents in the respective collector terminals,

wherein the drain current is an approximate sum of the binary weighted collector currents.

2. The high power digital to analog converter of claim 1 wherein

the depletion mode FET includes a gate terminal connected to a ground potential, and

the array of n transistors includes respective emitter terminals connected to the array of n switches for selectively connecting the respective emitter terminals to the ground potential.

3. The high power digital to analog converter of claim 1 wherein

the array of n switches are controlled by a digital word of n bits.

4. The high power digital to analog converter of claim 1 wherein

the depletion mode FET includes a gallium nitride, high electron mobility transistor.

5. The high power digital to analog converter of claim 1 wherein

the array of n switches includes an array of n-channel metal-oxide-semiconductor (NMOS) transistors, and

the array of n transistors includes an array of bipolar transistors or NMOS transistors.

6. The high power digital to analog converter of claim 1 wherein

the array of n switches are controlled, respectively, by n bits, and

the drain current provides an analog signal corresponding to the n bits.

7. The high power digital to analog converter of claim 6 including

a load coupled to the drain terminal for transmitting the analog signal as an RF power output signal.

8. The high power digital to analog converter of claim 7 wherein

the load is a matching transformer including a primary coil coupled to the drain terminal and a secondary coil coupled to an antenna.

9. The high power digital to analog converter of claim 6 including

a processor for providing the n bits as a core waveform to the n switches.

10. The high power digital to analog converter of claim 1 wherein

the array of n transistors includes respective base terminals tied together, and

a reference transistor having a base terminal tied to the respective base terminals of the array of n transistors for establishing a reference current to amplitude modulate the drain current.

11. A direct digital to antenna (DDA) transmitter comprising

an array of n transistors having n collector terminals for providing respective n collector currents, wherein the n collector currents are arranged in a binary sequence of I 0 , I 1 , I 2 , . . . I n-1 , and

a depletion mode field-effect transistor (FET) including a source terminal connected to the n collector terminals, and a drain terminal connected to a load for transmitting an analog signal,

wherein the array of n transistors are selectively activated by digital data to provide a selective binary sequence of I 0 , I 1 , I 2 , . . . I n-1 , and

the analog signal includes a value that is a predetermined constant value times an approximate sum of the selective binary sequence of I 0 , I 1 , I 2 , . . . I n-1 .

12. The DDA transmitter of claim 11 including

an array of n switches for receiving n bits of the digital data and selectively activating at least a portion of the n transistors in the array.

13. The DDA transmitter of claim 11 wherein

the depletion mode FET includes a base terminal connected to a ground potential, and

the array of n transistors includes n emitter terminals coupled to the ground potential.

14. The DDA transmitter of claim 13 wherein

an array of n switches are coupled between the n emitter terminals and the ground potential for selectively activating at least one of the n transistors in the array.

15. The DDA transmitter of claim 11 including

the array of n transistors includes respective base terminals tied together, and

a reference transistor having a base terminal is tied to the respective n base terminals of the array of n transistors for establishing a reference current to amplitude modulate the analog signal.

16. The DDA transmitter of claim 11 wherein

the depletion mode FET includes a gallium nitride, high electron mobility transistor.

17. The DDA transmitter of claim 11 wherein

the array of n switches includes an array of n-channel metal-oxide-semiconductors (NMOS) transistors, and

the array of n transistors includes an array of bipolar transistors or NMOS transistors.

18. The DDA transmitter of claim 11 wherein

the load coupled to the drain terminal is a matching transformer including a primary coil coupled to the drain terminal and a secondary coil configured for coupling to an antenna.

19. The DDA transmitter of claim 11 wherein

the load coupled to the drain terminal is configured for connection to a voltage supply, and

the array of n transistors have a breakdown voltage that is lower than a voltage provided by the voltage supply.

20. The DDA transmitter of claim 11 wherein

the array of n transistors are coupled to another array of n switches for selectively providing the digital data.