Predictive power gating with optional guard mechanism
View Patent ↗A mechanism is provided for predictively power gating a set of units within the data processing system. A second-level power gating controller monitors a set of events for each unit in a set of units within the data processing system. The second-level power gating controller identifies idle sequences of a predetermined set of cycles within the events from each unit where the unit is idle. The second-level power gating controller determines preceding sequences of a predetermined length that precede the idle sequences. The second-level power gating controller determines an accuracy of the preceding sequences. Responsive to the accuracy being above a threshold, the second-level power gating controller sends a permit command to a first-level power gating mechanism associated with the unit to permit power gating of the unit.
1. A method, in a data processing system, for predictively power gating a set of units within the data processing system, the method comprising:
monitoring, by a second-level power gating controller in the data processing system, a set of events for each unit in a set of units within the data processing system;
identifying, by the second-level power gating controller, idle sequences of a predetermined number of cycles within the events from each unit where the unit is idle;
determining, by the second-level power gating controller, preceding sequences of a predetermined length that precede the idle sequences;
determining, by the second-level power gating controller, an accuracy of the preceding sequences; and
responsive to the accuracy being above a threshold, sending, by the second-level power gating controller, a permit command to a first-level power gating mechanism associated with the unit, wherein the permit command allows the first-level power gating mechanism to power gate the unit.
2. The method of claim 1 , wherein the accuracy is determined using the following formula:
Accuracy
(
i
)
=
desiredOutcome
(
i
)
desiredOutcome
(
i
)
+
undesiredOutcome
(
i
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
3. The method of claim 1 , further comprising:
responsive to the accuracy being below the threshold, sending, by the second-level power gating controller, a prevent command to the first-level power gating mechanism associated with the unit, wherein the prevent command prevents the first-level power gating mechanism from power gating the unit.
4. The method of claim 1 , further comprising:
determining, by the second-level power gating controller, a predictability of the preceding sequences;
determining, by the second-level power gating controller, a detectability of the preceding sequences; and
using the predictability and the detectability, calculating, by the second-level power gating controller, an optimized length that replaces the predetermined length.
5. The method of claim 4 , wherein the predictability is determined using the following formula:
P
=
∑
i
∈
Ω
desiredOutcome
(
i
)
∑
i
∈
Ω
desiredOutcome
(
i
)
+
undesiredOutcome
(
i
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
6. The method of claim 4 , wherein the detectability is determined using the following formula:
D
=
∑
i
∈
Ω
desiredOutcome
(
i
)
∑
j
∈
Λ
desiredOutcome
(
j
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
7. The method of claim 1 , wherein the set of events is a historical sequence of events indicating states of the unit, wherein the states are either idle or active.
8. A computer program product comprising a computer readable storage medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:
monitor a set of events for each unit in a set of units within the data processing system;
identify idle sequences of a predetermined number of cycles within the events from each unit where the unit is idle;
determine preceding sequences of a predetermined length that precede the idle sequences;
determine an accuracy of the preceding sequences; and
responsive to the accuracy being above a threshold, send a permit command to a first-level power gating mechanism associated with the unit, wherein the permit command allows the first-level power gating mechanism to power gate the unit.
9. The computer program product of claim 8 , wherein the accuracy is determined
using the following formula:
Accuracy
(
i
)
=
desiredOutcome
(
i
)
desiredOutcome
(
i
)
+
undesiredOutcome
(
i
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
10. The computer program product of claim 8 , wherein the computer readable program further causes the computing device to:
responsive to the accuracy being below the threshold, send a prevent command to the first-level power gating mechanism associated with the unit, wherein the prevent command prevents the first-level power gating mechanism from power gating the unit.
11. The computer program product of claim 8 , wherein the computer readable program further causes the computing device to:
determine a predictability of the preceding sequences;
determine a detectability of the preceding sequences; and
using the predictability and the detectability, calculate an optimized length that replaces the predetermined length.
12. The computer program product of claim 11 , wherein the predictability is determined using the following formula:
P
=
∑
i
∈
Ω
desiredOutcome
(
i
)
∑
i
∈
Ω
desiredOutcome
(
i
)
+
undesiredOutcome
(
i
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
13. The computer program product of claim 11 , wherein the detectability is determined using the following formula:
D
=
∑
i
∈
Ω
desiredOutcome
(
i
)
∑
j
∈
Λ
desiredOutcome
(
j
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
14. The computer program product of claim 8 , wherein the set of events is a historical sequence of events indicating states of the unit, wherein the states are either idle or active.
15. An apparatus, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
monitor a set of events for each unit in a set of units within the data processing system;
identify idle sequences of a predetermined number of cycles within the events from each unit where the unit is idle;
determine preceding sequences of a predetermined length that precede the idle sequences;
determine an accuracy of the preceding sequences; and
responsive to the accuracy being above a threshold, send a permit command to a first-level power gating mechanism associated with the unit, wherein the permit command allows the first-level power gating mechanism to power gate the unit.
16. The apparatus of claim 15 , wherein the accuracy is determined using the following formula:
Accuracy
(
i
)
=
desiredOutcome
(
i
)
desiredOutcome
(
i
)
+
undesiredOutcome
(
i
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
17. The apparatus of claim 15 , wherein the instructions further cause the processor to:
responsive to the accuracy being below the threshold, send a prevent command to the first-level power gating mechanism associated with the unit, wherein the prevent command prevents the first-level power gating mechanism from power gating the unit.
18. The apparatus of claim 15 , wherein the instructions further cause the processor to:
determine a predictability of the preceding sequences;
determine a detectability of the preceding sequences; and
using the predictability and the detectability, calculate an optimized length that replaces the predetermined length.
19. The apparatus of claim 18 , wherein the predictability is determined using the following formula:
P
=
∑
i
∈
Ω
desiredOutcome
(
i
)
∑
i
∈
Ω
desiredOutcome
(
i
)
+
undesiredOutcome
(
i
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.
20. The apparatus of claim 18 , wherein the detectability is determined using the following formula:
D
=
∑
i
∈
Ω
desiredOutcome
(
i
)
∑
j
∈
Λ
desiredOutcome
(
j
)
wherein the desiredOutcome represents a number of desired sequences that have occurred in a specified corner and wherein the “undesiredOutcome” represents a number of sequences that have occurred in the specified corner which are different from the desired sequences.