IP Library Granted Patent US 8,044,482
Granted Patent B2
US 8,044,482 · App. 12/540,043 · Granted Oct 25, 2011

Semiconductor device

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,044,482
App. No.
12/540,043
Granted
Oct 25, 2011
Kind
B2
Abstract

A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.

Claims (27)

1. A semiconductor device comprising:

an insulating film formed on a semiconductor substrate;

a plurality of contact wirings including copper formed in the insulating film so that the plurality of contact wirings are separated from one another;

a protective film formed on the plurality of contact wirings and the insulating film;

an opening portion formed in the protective film, the plurality of contact wirings being exposed through the opening portion; and

an electrode pad formed in the opening portion, the electrode pad being electrically connected to the plurality of contact wirings,

wherein there are no insulating films between the insulating film and a part of the electrode pad located directly below the opening portion, and

an upper surface of a part of the insulating film located below the opening portion is lower than an upper surface of at least one of the plurality of the contact wirings.

2. The semiconductor device of claim 1 , wherein at least one of the plurality of contact wirings is in the shape of a ring.

3. The semiconductor device of claim 2 , wherein the ring-shaped contact wiring overlaps an edge of the opening portion.

4. The semiconductor device of claim 1 , wherein the plurality of contact wirings do not overlap an edge of the opening portion.

5. The semiconductor device of claim 1 , wherein the plurality of contact wirings include a first contact wiring, and a second contact wiring smaller than the first contact wiring.

6. The semiconductor device of claim 5 , wherein the first contact wiring is provided below a peripheral portion of the opening portion, and the second contact wiring is provided below a center portion of the opening portion.

7. The semiconductor device of claim 1 , wherein at least one of the plurality of contact wirings is in the shape of a rectangle whose corner portions are beveled.

8. The semiconductor device of claim 1 , wherein

a lower-layer wiring is formed between the semiconductor substrate and the insulating film,

at least one of the plurality of the contact wirings and the lower-layer wiring are connected with a via, and

in a surface in which the at least one of the plurality of the contact wirings and the via are connected together, an area of the at least one of the plurality of the contact wirings is larger than that of the via.

9. The semiconductor device of claim 8 , wherein the lower-layer wiring extends to a region outside the opening portion.

10. The semiconductor device of claim 1 , wherein

the plurality of contact wirings are made of copper or a copper alloy, and

the electrode pad is made of aluminum or an aluminum alloy.

11. The semiconductor device of claim 1 , wherein at least one of the plurality of the contact wirings substantially has a quadrilateral shape.

12. The semiconductor device of claim 1 , wherein at least one of the plurality of the contact wirings substantially has a square shape.

13. The semiconductor device of claim 1 , wherein

a wiring is formed in a part of the insulating film located in a region outside the opening portion, and

a width of the wiring is larger than a width of each of the plurality of the contact wirings.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2009
From: OTA, YUKITOSHI; HIRANO, HIROSHIGE; ITOU, YUTAKA; KOIKE, KOJI
To: PANASONIC CORPORATION
Reel/Frame 023477/0506 →
Priority Claims (1)
JP 2008-263592 · Oct 10, 2008 · national
Continuity (1)
Related Publication 20100090344A1 · Apr 15, 2010