IP Library Granted Patent US 8,355,570
Granted Patent B2
US 8,355,570 · App. 12/540,330 · Granted Jan 15, 2013

Systems and methods for raster-to-block converter

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Quick Facts
Patent No.
US 8,355,570
App. No.
12/540,330
Granted
Jan 15, 2013
Kind
B2
Abstract

A raster to block converter and equivalently a block to raster converter can be implemented using enough memory to contain a single image band, that is a band of pixels of height equal to a single block but spanning the entire width of an image. The raster to block converter can operate at full rate so that as soon as a pixel is read out from the memory a new pixel can be stored in its place. The location of a pixel can be tracked using a mapping involving basic modular arithmetic. This raster to block converter is scalable so that it can work with any size image and block size.

Claims (197)

1. A method of processing an image comprising:

determining a memory location from an image band location associated with a first pixel having first pixel data;

retrieving the first pixel data from a memory at the memory location;

outputting the first pixel data to an outbound stream of pixel data;

receiving second pixel data from an inbound stream;

storing the second pixel data to the memory at the memory location,

wherein the determining the memory location comprises:

separating the image band location into an image sliver part i, a pixel part, and an offset part on the basis of a predetermined block size;

mapping the image sliver part to a converted image sliver part addr(i) by the equation

addr

(

i

)

=

{

δ

i

modulo

(

w

-

1

)

w

-

1

if

i

w

-

1

otherwise

,

where w is the width of the image and δ is a multiplicative factor; and

combining the converted image sliver part, the pixel part and the offset part into the memory location; and

multiplying δ by a predetermined factor modulo (w−1) after all pixels in an image band have been retrieved.

2. The method of claim 1 , wherein the inbound stream is in raster order;

the outbound stream is in block order;

the predetermined block has a width; and

the predetermined factor is w divided by the width.

3. A method of claim 2 , further comprising:

performing a discrete cosine transform on the outbound stream of pixel data to produce transformed image data;

quantizing the image transformed image data; and

entropy encoding the transformed image data.

4. The method of claim 1 , wherein the inbound stream is in block order;

the outbound stream is in raster order;

the predetermined block has a height; and

the predetermined factor is the height.

5. The method of claim 4 , further comprising:

entropy decoding encoded image data;

dequantizing the encoded image data; and

performing an inverse DCT on the encoded image data to produce the inbound stream of pixel data.

6. An image processing apparatus comprising:

a reordering converter for reordering an image from an inbound stream of pixel data into an outbound stream of pixel data comprising:

a memory;

control logic which retrieves first pixel data from a memory location in the memory and places the first pixel data on the outbound stream of pixel data and receives second pixel data from the inbound stream and stores the second pixel data into the memory at the memory location;

an address converter, which separates an image band location associated with the first pixel data into an image sliver part i, a pixel part, and an offset part on the basis of a predetermined block size; maps the image sliver part is converted by the equation

addr

(

i

)

=

{

δ

i

modulo

(

w

-

1

)

w

-

1

if

i

w

-

1

otherwise

into image sliver part addr(i), where w is the width of the image and δ is a multiplicative factor; combines the converted image sliver part, the pixel part and the offset part into the memory location; and multiplies δ by a predetermined factor after all pixels in an image band have been retrieved.

7. The image processing apparatus of claim 6 , wherein the memory comprises a frame buffer.

8. The image processing apparatus of claim 6 , wherein the inbound stream is in raster order;

the outbound stream is in block order;

the predetermined block has a width; and

the predetermined factor is w divided by the width.

9. The image processing apparatus of claim 8 , further comprising:

a DCT module coupled to the reordering converter;

a quantizer coupled to the DCT module; and

an entropy coder coupled to the quantizer.

10. The image processing apparatus of claim 8 , further comprising:

a DCT module coupled to the reordering converter,

a quantizer coupled to the DCT module,

a dequantizer coupled to the quantizer,

an IDCT module coupled to the dequantizer;

a motion estimator; and

a motion compensator coupled to the motion estimator.

11. The image processing apparatus of claim 8 , further comprising:

a second reordering converter coupled to the motion estimator.

12. The image processing apparatus of claim 6 , wherein the inbound stream is in block order;

the outbound stream is in raster order;

the predetermined block has a height; and

the predetermined factor is the height.

13. The image processing apparatus of claim 12 , further comprising:

a iDCT module coupled to the reorder converter;

a dequantizer coupled to the DCT module; and

an entropy decoder coupled to the dequantizer.

14. The image processing apparatus of claim 12 , further comprising:

a iDCT module coupled to the reorder converter;

a dequantizer coupled to the DCT module;

an entropy decoder coupled to the dequantizer; and

a motion compensator coupled to the entropy decoder.

15. An image processing apparatus comprising:

a memory;

means for converting an image band location associated with a first pixel having first pixel data into a memory location, comprising:

means for separating the image band location into an image sliver part i, a pixel part, and an offset part on the basis of a predetermined block size;

means for mapping the image sliver part to a converted image sliver part addr(i) by the equation

addr

(

i

)

=

{

δ

i

modulo

(

w

-

1

)

w

-

1

if

i

w

-

1

otherwise

,

where w is the width of the image and δ is a multiplicative factor;

means for combining the converted image sliver part, the pixel part and the offset part into the memory location; and

means for multiplying δ by a predetermined factor after all pixels in the first image band have been retrieved;

means for retrieving the first pixel data from the memory at the memory location;

means for outputting the first pixel data to an outbound stream of pixel data;

means for receiving second pixel data from an inbound stream;

means for storing the second pixel data to the memory at the memory location.

16. The image processing apparatus of claim 15 , wherein the inbound stream is in raster order;

the outbound stream is in block order;

the predetermined block has a width; and

the predetermined factor is w divided by the width.

17. The image processing apparatus of claim 16 , further comprising:

means for performing a discrete cosine transform on the image to produce transformed image data;

means for quantizing the image transformed image data; and

means for entropy encoding the transformed image data.

18. The image processing apparatus of claim 15 , wherein the inbound stream is in block order;

the outbound stream is in raster order;

the predetermined block has a height; and

the predetermined factor is the height.

19. The image processing apparatus of claim 18 , further comprising:

means for entropy decoding the encoded image data;

means for dequantizing the encoded image data; and

performing an inverse DCT on the encoded image data to produce an image.

20. The image processing apparatus of claim 18 , further comprising means for entropy decoding the encoded image data.

Assignments (10)
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2017
From: CONEXANT SYSTEMS, LLC
To: SYNAPTICS INCORPORATED
Reel/Frame 043786/0267 →
CHANGE OF NAME Recorded Jun 26, 2017
From: CONEXANT SYSTEMS, INC.
To: CONEXANT SYSTEMS, LLC
Reel/Frame 042986/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: LAKESTAR SEMI INC.
To: CONEXANT SYSTEMS, INC.
Reel/Frame 038803/0693 →
CHANGE OF NAME Recorded May 20, 2016
From: CONEXANT SYSTEMS, INC.
To: LAKESTAR SEMI INC.
Reel/Frame 038777/0885 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: CONEXANT SYSTEMS, INC.; CONEXANT, INC.; CONEXANT SYSTEMS WORLDWIDE, INC.; BROOKTREE BROADBAND HOLDING, INC.
Reel/Frame 038631/0452 →
SECURITY AGREEMENT Recorded Jun 7, 2010
From: CONEXANT SYSTEMS, INC.; CONEXANT, INC.; CONEXANT SYSTEMS WORLDWIDE, INC.; BROOKTREE BROADBAND HOLDING, INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 024492/0339 →
RELEASE OF SECURITY INTEREST Recorded Mar 2, 2010
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A. (FORMERLY, THE BANK OF NEW YORK TRUST COMPANY, N.A.)
To: CONEXANT SYSTEMS, INC.
Reel/Frame 024014/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2009
From: KARSANBHAI, MANHAR, MR; BROOKS, JOHN M, MR
To: CONEXANT SYSTEMS, INC.
Reel/Frame 023098/0620 →
SECURITY AGREEMENT Recorded Aug 13, 2009
From: CONEXANT SYSTEMS, INC.
To: THE BANK OF NEW YORK TRUST COMPANY, N.A.
Reel/Frame 023098/0626 →