Separate memories and address busses to store data and signature

1. A device, comprising:

a first memory;

a second memory;

a core logic unit, coupled to the first memory via a first address line and coupled to the second memory via a second address line, wherein the core logic unit is programmed to read from and write to the first and second memories;

a first signature generator logic, configured to compute a first signature from data written to the first memory, coupled to the second memory to store the first signature in the second memory;

a second signature generator logic, configured to compute a second signature from data read from the first memory; and

a comparator logic, coupled to the second memory and the second signature generator logic, indicating an error condition to the core logic unit if the first signature does not match the second signature

wherein the first signature is computed as part of writing to the first memory.

2. The device of claim 1 , wherein the second memory, the core logic, the first signature generator logic, the second signature generator logic, and the comparator logic are contained in a single chip.

3. The device of claim 1 , wherein the first memory, the second memory, the core logic, the first signature generator logic, the second signature generator logic, and the comparator logic are contained in a single chip.

4. The device of claim 1 , wherein the first memory and the second memory are external to a chip containing the core logic, the first and second signature generator logics, and the comparator logic.

5. The device of claim 1 , wherein the data are stored in the first memory at an address indicated on the first address line, and the first signature is stored in the second memory at the same address, indicated on the second address line.

6. The device of claim 1 , wherein the data are stored in the first memory and the first signature is stored in the second memory concurrently.

7. The device of claim 1 , further comprising:

an error detection and correction logic coupled to the first memory,

wherein the error detection and correction logic detects errors in data read from the first memory before the second signature logic computes the second signature.

8. A method, comprising:

comparing a first signature computed from data written to a first memory using a first address line with a second signature computed from data read from the first memory; and

storing the first signature in a second memory using a second address line,

wherein the first signature is computed as part of writing to the first memory.

9. The method of claim 8 , wherein comparing a first signature computed from data written to a first memory using a first address line with a second signature computed from data read from the first memory comprises:

computing the first signature from the data;

writing the data to the first memory at a first address;

reading the data from the first memory at the first address;

reading the first signature from the second memory at a second address; and

computing the second signature from the data as read from the first memory.

10. The method of claim 9 , wherein the act of writing the data to the first memory and the act of storing the first signature are performed concurrently.

11. The method of claim 9 , wherein the act of reading the data from the first memory and the act of reading the first signature from the second memory are performed concurrently.

12. The method of claim 8 , further comprising indicating an error condition if the first signature and the second signature do not match.

13. The method of claim 8 , further comprising:

detecting and correcting data errors for data read from the first memory responsive to an error detection and correction code stored with the data in the first memory.

14. The method of claim 8 , wherein the first memory is external to a chip containing logic for performing the act of comparing a first signature computed from data written to a first memory with a second signature computed from data read from the first memory and the act of storing the first signature in a second memory.

15. The method of claim 8 , wherein the second memory is internal to a chip containing logic for performing the act of comparing a first signature computed from data written to a first memory with a second signature computed from data read from the first memory and the act of storing the first signature in a second memory.

16. The method of claim 8 , wherein the first signature and the second signature are cyclic redundancy codes using a tenth order polynomial.

17. The method of claim 8 , wherein the data are written to the first memory at a first address and the first signature is written to the second memory at the first address.

18. A device comprising:

a first memory; and

a field programmable gate array (FPGA), coupled to the first memory using a first address line, the FPGA comprising:

a second memory, internal to the FPGA, addressed using a second address line; and

logic to perform the acts of:

comparing a first signature computed from data written to the first memory with a second signature computed from data read from the first memory; and

storing the first signature in the second memory,

wherein the first signature is computed as part of writing to the first memory.

19. The device of claim 18 , wherein the act of comparing comprises:

computing the first signature from the data;

writing the data to the first memory at a first address;

reading the data from the first memory at the first address;

reading the first signature from the second memory at the first address;

computing the second signature from the data as read from the first memory; and

generating an error indication if the first signature does not match the second signature.