IP Library Granted Patent US 8,212,300
Granted Patent B2
US 8,212,300 · App. 12/545,469 · Granted Jul 3, 2012

Semiconductor device

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,212,300
App. No.
12/545,469
Granted
Jul 3, 2012
Kind
B2
Abstract

After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.

Claims (19)

1. A semiconductor device comprising:

a semiconductor substrate;

a transistor formed in the semiconductor substrate;

a first insulating film formed on the semiconductor substrate to cover the transistor;

an etching stopper film formed on the first insulating film;

a first plug formed by filling a conductive material into a contact hole extending from an upper surface of the etching stopper film and reaching an impurity region constituting the transistor;

a SiON film formed on the etching stopper film;

a hydrogen barrier film formed over the SiON film;

a ferroelectric capacitor formed on the hydrogen barrier film;

a second insulating film formed on the hydrogen barrier film to cover the ferroelectric capacitor; and

a second plug formed by filling a conductive material into a contact hole extending from an upper surface of the second insulating film and reaching the first plug.

2. The semiconductor device according to claim 1 , wherein a metal silicide layer is formed on the impurity region.

3. The semiconductor device according to claim 1 , wherein the metal silicide layer is selected from cobalt silicide or titanium silicide.

4. The semiconductor device according to claim 1 , wherein the first plug reaches the metal silicide layer.

5. The semiconductor device according to claim 1 , wherein the etching stopper film has a thickness of 20 nm to 150 nm.

6. The semiconductor device according to claim 5 , wherein the etching stopper film is formed of silicon oxynitride or silicon nitride.

7. The semiconductor device according to claim 1 , wherein the etching stopper film is formed of a metal oxide.

8. The semiconductor device according to claim 7 , wherein the etching stopper film has a thickness equal to or less than 100 nm.

9. The semiconductor device according to claim 1 , wherein the ferroelectric capacitor has a lower electrode, a ferroelectric film and an upper electrode comprised of a first and second IrO 2 film stack.

Assignments (3)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2009
From: NAGAI, KOUICHI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023362/0988 →
Continuity (2)
Continuation PCTJP2007053138 · Feb 21, 2007
Related Publication 20100019348A1 · Jan 28, 2010