Analog computation

1. In a device having a first group of capacitors and a second group of capacitors, a method comprising:

inducing charges on respective capacitors in the first group of capacitors, each induced charge being determined by a corresponding input signal;

redistributing charge among capacitors in each of a first plurality of sets of capacitors, each of the sets of capacitors including at least one capacitor from the first group of capacitors and one capacitor from the second group of capacitors;

redistributing charge among capacitors in each of a second plurality of sets of capacitors, each set in the second plurality of sets of capacitors including a corresponding disjoint subset of the second group of capacitors; and

determining output signals, including determining each output signal according to a charge on a capacitor in a corresponding set of the second plurality of sets of capacitors.

2. The method of claim 1 , wherein at least some sets of the first plurality of sets of capacitors further each includes a capacitor not in the first group or the second group of capacitors.

3. The method of claim 2 , wherein in each of the at least some sets of the first plurality of sets of capacitors, the capacitor not in the first or the second group includes a compensation capacitor switchably coupled in series with at least one capacitor from the first group and with at least one capacitor from the second group.

4. The method of claim 2 , wherein in each of the at least some sets of the first plurality of sets of capacitors, the capacitor not in the first or the second group includes a compensation capacitor switchably coupled in parallel with at least one capacitor from the first group of capacitors.

5. The method of claim 2 , wherein the total capacitance of capacitors in each set of the first plurality of sets of capacitors is equal.

6. The method of claim 2 , wherein the total capacitance of capacitors in each set of the second plurality of sets of capacitors is equal.

7. The method of claim 1 , wherein each output signal represents an algebraic function of a subset of the input signals, the algebraic function having coefficients determined at least in part by a configuration of the first and second plurality of capacitors.

8. The method of claim 7 , wherein the algebraic function includes a transform of the input signals.

9. The method of claim 8 wherein the transform represents a frequency domain transform.

10. The method of claim 7 , wherein the algebraic function includes a weighted summation.

11. The method of claim 1 , wherein the input signals include one or more voltage encoded signals.

12. The method of claim 1 , further comprising controlling a capacitance of at least one variable capacitor in the first and the second pluralities of sets of capacitors.

13. The method of claim 1 , further comprising:

redistributing charge among capacitors in each of a third plurality of sets of capacitors, each set in the third plurality of sets of capacitors including a at least one capacitor from the second group of capacitors and one capacitor from a third group of capacitors.

14. The method of claim 1 , wherein at least some sets of the first plurality of sets of capacitors further each includes a gain buffer coupled between the first group and the second group of capacitors.

15. A circuit comprising:

a first group of capacitors;

a second group of capacitors;

an input circuit configured for accepting a set of input signals;

switches for forming sets of capacitors among which charge may redistribute, the switches being configurable in configurations including:

a first configuration for inducing a charge on each capacitor in the first group of capacitors according to a corresponding one of the input signals;

a second configuration for forming a first plurality of sets of capacitors, each set of capacitors including at least one capacitor from the first group of capacitors and one capacitor from the second group of capacitors, and

a third configuration for forming a second plurality of sets of capacitors, each set in the second plurality of sets of capacitors including a corresponding disjoint subset of the second group of capacitors;

an output circuit for determining output signals, each output signal being determined according to a charge on a capacitor in a corresponding set of the second plurality of sets of capacitors.

16. The circuit of claim 15 further comprising, in addition to the first group and the second group of capacitors, a third group of capacitors, wherein at least some sets of capacitors formed by the switches further each includes a capacitor from the third group of capacitors.

17. A circuit comprising:

an input circuit configured for accepting a set of input signals;

a first group of capacitors;

switches for forming sets of capacitors among which charge may redistribute, the switches being configurable in configurations including:

a first configuration for inducing, for each capacitor in the first group of capacitors, a charge according to a corresponding one of the input signals; and

a second configuration for forming a plurality of sets of capacitors, each set of capacitors including a corresponding disjoint plurality of the first group of capacitors and at least one capacitor not from the first group of capacitors; and

an output circuit for determining output signals, each output signal being determined according to a charge on a capacitor in a corresponding set of the plurality of sets of capacitors.

18. The circuit of claim 17 , wherein the total capacitance of capacitors in each set of the plurality of sets of capacitors is equal.

19. The circuit of claim 17 , wherein the first and second sets of capacitors are configured to have desired capacitance for performing a real fast Fourier Transform (FFT) computation.

20. In a device having a plurality of storage sections each section having a respective plurality of capacitors, a method comprising:

inducing charges on respective capacitors in an initial storage section, each induced charge being determined by a corresponding input signal;

in each of one or more successive processing stages, forming a pair of storage sections for charge redistribution, including in each stage, switchably coupling capacitors from the corresponding pair of storage sections to form a group of one or more sets of capacitors among which charge redistributes; and

determining output signals according to charges on capacitors in a final storage section.

21. An integrated circuit comprising:

a set of two or more storage sections, each storage section having a plurality of capacitors for storing charge;

a configurable circuitry coupled to the storage sections for enabling charge redistribution among capacitors in different storage sections, the configurable circuitry including a plurality of switches each being coupled to at least two capacitors each capacitor from a different storage section; and

a control logic for configuring the configurable circuitry to form, in each of one or more successive processing stages, a respective pair of storage sections, wherein in each stage, the control logic is configured to selectively activate subsets of switches in the configurable circuitry to couple capacitors from a formed pair of storage sections to form a group of one or more sets of capacitors among which charge redistributes.