Multi-level security computing system
View Patent ↗According to one embodiment, a computing system includes two or more opto-electrical isolators coupling a corresponding two or more memory devices to a processor. Each memory device is electrically isolated from each other and configured to store data or instructions executed by the processor. Each opto-electrical isolator selectively couples its associated memory device to the processor such that only one of the two or more memory devices are writable by the processor at any instant of time.
1. A computer-implemented system comprising:
two or more opto-electrical isolators that couple a corresponding two or more memory devices to a processor, a first of the two or more opto-electrical isolator being disposed between a first of the two or more memory devices and the processor and a second of the two or more opto-electrical isolator being disposed between a second of the two or more memory devices and the processor, the first and second of the two or more memory devices separated by the first and second of the two or more opto-electrical isolators and the processor, the two or more opto-electrical isolators, two or more memory devices, and processor configured in a communication device, each memory device being electrically isolated from each other and operable to store data or instructions executed by the processor, a first memory device of the two or more memory devices has a security level that is more confidential than the security level of a second memory device of the two or more memory devices;
the opto-electrical isolator associated with the first memory device operable to:
inhibit read and write access of the first memory device when the processor accesses the second memory device; and
the opto-electrical isolator associated with the second memory device operable to:
inhibit write access of the second memory device when the processor accesses the first memory device.
2. A computer-implemented system comprising:
two or more opto-electrical isolators that couple a corresponding two or more memory devices to a processor, a first of the two or more opto-electrical isolator being disposed between a first of the two or more memory devices and the processor and a second of the two or more opto-electrical isolator being disposed between a second of the two or more memory devices and the processor, the first and second of the two or more memory devices separated by the first and second of the two or more opto-electrical isolators and the processor, each memory device being electrically isolated from each other and operable to store data or instructions executed by the processor, each opto-electrical isolator operable to:
selectively couple its associated each memory device to the processor such that only one of the two or more memory devices are writable by the processor at any instant of time.
3. The computer-implemented system of claim 2 , wherein each opto-electrical isolator comprises a read inhibit portion that is operable to selectively inhibit read access from its associated memory device and a write inhibit portion that is operable to selectively inhibit write access to its associated memory device.
4. The computer-implemented system of claim 2 , wherein a first memory device of the two or more memory devices has a security level that is less confidential than the security level of a second memory device of the two or more memory devices, the opto-electrical isolator associated with the first memory device operable to inhibit write access of the first memory device when the processor accesses the second memory device, the opto-electrical isolator associated with the second memory device operable to inhibit read access and write access of the second memory device when the processor accesses the first memory device.
5. The computer-implemented system of claim 2 , wherein the processor, the two or more memory devices and associated opto-electrical isolators are configured in a communication device.
6. The computer-implemented system of claim 2 , wherein each opto-electrical isolator is controlled by the processor.
7. The computer-implemented system of claim 2 , further comprising a key card coupled to the processor, a first memory device of the two or more memory devices has a security level that is less confidential than the security level of a second memory device of the two or more memory devices, the processor operable to selectively couple to the second memory by execution of a login file stored in the key card.
8. The computer-implemented system of claim 2 , wherein each opto-electrical isolator is controlled by a controlling system external to the processor.
9. The computer-implemented system of claim 2 , wherein the processor is operable to purge, using one or both of the opto-electrical isolators, the data or instructions in one or both of the two memory devices.
10. The computer-implemented system of claim 9 , wherein the processor is coupled to a wireless transceiver, the processor operable to purge the data or instructions in response to one or more remote signals received from the wireless transceiver.
11. The computer-implemented system of claim 2 , wherein the processor is operable to encrypt data or instructions that are written to one or both of the memory devices and decrypt data or instructions that are read from the one or both memory devices.
12. A computer-implemented method comprising:
selectively coupling two or more memory devices to a processor using a corresponding two or more opto-electrical isolators, a first of the two or more opto-electrical isolator being disposed between a first of the two or more memory devices and the processor and a second of the two or more opto-electrical isolator being disposed between a second of the two or more memory devices and the processor, the first and second of the two or more memory devices separated by the first and second of the two or more opto-electrical isolators and the processor such that only one of the two or more memory devices are writable by the processor at any instant of time, the two or more memory devices electrically isolated from each other and operable to store data or instructions that are executed on the processor.
13. The computer-implemented method of claim 12 , further comprising:
selectively inhibiting read access, using a read inhibit portion of one opto-electrical isolator, from its associated memory device; and
selectively inhibiting write access, using a write inhibit portion of the one opto-electrical isolator, from its associated memory device.
14. The computer-implemented method of claim 12 , further comprising:
inhibiting, using a first opto-electrical isolator, read access and write access of a first memory device associated with the first opto-electrical isolator, when the processor has read access and write access to a second memory device through a second opto-electrical isolator associated with the second memory device, the first memory device having a security level that is more confidential than the security level of the second memory device; and
inhibiting, using the second opto-electrical isolator, write access of the second memory device when the processor has read access and write access to the first memory device through the first opto-electrical isolator.
15. The computer-implemented method of claim 12 , wherein the processor, the two or more memory devices and associated opto-electrical isolators are configured in a communication device.
16. The computer-implemented method of claim 12 , further comprising controlling the two or more opto-electrical isolators using the processor.
17. The computer-implemented method of claim 12 , further comprising selectively coupling to a second memory of the two or more memory devices by executing a login file store in a key card coupled to the processor, the second memory device of the two or more memory devices has a security level that is more confidential than the security level of a first memory device of the two or more memory devices.
18. The computer-implemented method of claim 12 , further comprising controlling the two or more opto-electrical isolators using a controlling system external to the processor.
19. The computer-implemented method of claim 12 , further comprising purging, using one or both of the opto-electrical isolators, the data or instructions in one or both of the two memory devices.
20. The computer-implemented method of claim 19 , further comprising purging the data or instructions using one or more remote signals received from a wireless transceiver, the wireless transceiver coupled to the processor.
21. The computer-implemented method of claim 12 , further comprising:
encrypting the data or instructions that are written to the one or both of the memory devices; and
decrypting the data or instructions that are read from the one or both memory devices.