Digital memory with controllable input/output terminals

1. A digital memory unit, comprising:

an input/output (I/O) terminal having an I/O driver configured to selectively drive a digital value; and

a detector coupled to the I/O driver, wherein the detector is configured to:

detect the digital value;

compare the digital value with a digital value previously provided to the I/O terminal; and

conditionally shut off power to the I/O driver based, at least in part, on a result of the comparison of the digital value and the previously provided digital value.

2. The digital memory unit of claim 1 , wherein the detector is further configured to shut off power to the I/O driver upon a determination that the result of the comparison indicates that the compared digital values are the same.

3. The digital memory unit of claim 1 , wherein the detector comprises a clock toggle switch.

4. The digital memory unit of claim 1 , wherein the previously provided digital value immediately precedes the digital value.

5. The digital memory unit of claim 1 , wherein the detector comprises a latch configured to hold the previously provided digital value.

6. The digital memory unit of claim 1 , wherein the digital value and the previously provided digital value comprise address values.

7. The digital memory unit of claim 1 , wherein the digital value and the previously provided digital value comprise data values.

8. The digital memory unit of claim 1 , wherein:

the I/O terminal further comprises a second I/O driver configured to selectively drive a second digital value; and

the detector is further configured to:

detect the second digital value;

compare the second digital value with a second digital value previously provided to the I/O terminal; and

conditionally shut off power to the second I/O driver based, at least in part, on a result of the comparison of the digital value and the previously provided second digital value.

9. The digital memory unit of claim 1 , wherein:

the I/O terminal further comprises a second I/O driver configured to selectively drive a second digital value;

the digital memory unit further comprises a second detector; and

the second detector is coupled to the second I/O driver, wherein the second detector is configured to:

detect the second digital value;

compare the second digital value with a second digital value previously provided to the I/O terminal; and

conditionally shut off power to the second I/O driver based, at least in part, on a result of the comparison of the second digital value and the previously provided second digital value.

10. The digital memory unit of claim 1 , further comprising another I/O terminal having at least one other I/O driver, wherein the at least one other I/O driver is configured to drive another digital value, and wherein the detector is further coupled to the at least one other I/O driver to conditionally shut off power to the at least one other I/O driver based, at least in part, on the other digital value.

11. The digital memory unit of claim 1 , further comprising another I/O terminal having at least one other I/O driver, wherein the at least one other I/O driver is configured to drive another digital value, and wherein the digital memory unit further comprises another detector coupled to the at least one other I/O driver to conditionally shut off power to the at least one other I/O driver based, at least in part, on the other digital value.

12. The digital memory unit of claim 1 , wherein the digital memory unit is a memory bank comprising multiple memory cells, and wherein the I/O terminal is coupled to at least one of the memory cells.

13. A system, comprising:

a digital memory bank including a plurality of input/output (I/O) terminals and memory cells coupled to the I/O terminals, wherein each I/O terminal has one or more I/O drivers;

a controller coupled to the digital memory bank and configured to control reads from, and writes to, the digital memory bank; and

a detector coupled to at least one I/O driver from one of the plurality of I/O terminals, wherein the detector is configured to detect a digital value provided to the one of the I/O terminals, and wherein the detector is further configured to compare the digital value with a digital value previously provided to the I/O terminal and to conditionally shut off power to the at least one I/O driver based, at least in part, on a result of the comparison of the digital value with the previously provided digital value.

14. The system of claim 13 , wherein the detector is further configured to conditionally shut off power to the at least one I/O driver if the digital value and the previously provided digital value are the same.

15. The system of claim 13 , wherein the digital value and the previously provided digital value comprise address values.

16. The system of claim 13 , wherein the digital value and the previously provided digital value comprise data values.

17. The system of claim 13 , wherein:

the detector is further coupled to another I/O driver for the I/O terminals; and

the detector is further configured to conditionally shut off power to the other I/O driver based, at least in part, on a result of a comparison between another digital value provided to the other I/O driver and another digital value previously provided to the other I/O driver.

18. The system of claim 13 , wherein:

the system further comprises at least one other detector coupled to another I/O driver for at least one of the I/O terminals; and

the other detector is configured to conditionally shut off power to the other I/O driver based, at least in part, on a result of a comparison between another digital value provided to the other I/O driver and another digital value previously provided to the other I/O driver.

19. An apparatus, comprising:

first means for driving input, or output, of digital values into, or out of, the apparatus; and

second means for detecting a current digital value provided to the first means, for comparing the current digital value with a digital value previously provided to the first means, and for conditionally shutting off power to the first means based, at least in part, on a result of the comparison.

20. The apparatus of claim 19 , wherein the digital value is an address value or a data value.

21. A method of operating digital memory, the method comprising:

detecting a digital value provided to an input/output (I/O) terminal; and

conditionally shutting off power to an I/O driver associated with the I/O terminal based, at least in part, on whether the digital value differs from another digital value previously provided to the I/O terminal.

22. The method of claim 21 , wherein said conditionally shutting off power to an I/O driver comprises shutting off power to the I/O driver when the digital value and the previously provided digital value are the same.

23. The method of claim 21 , further comprising providing the digital value and the previously provided digital value to the I/O terminal.

24. An article of manufacture, comprising a storage medium including a plurality of hardware design language instructions, or a compilation of the hardware design language instructions, wherein the hardware design language instructions are configured to specify an implementation of the digital memory unit as set forth in claim 1 as an integrated circuit.

25. The article of manufacture of claim 24 , wherein the hardware design language instructions comprises a selected one of VHDL or Verilog, or wherein the compilation is in GDS format.

26. The digital memory unit of claim 1 , wherein the detector is further configured to conditionally shut off power to the I/O driver at some point during a drive operation of the digital value by the I/O driver.

27. The system of claim 13 , wherein the detector is further configured to conditionally shut off power to the at least one I/O driver after the at least one I/O driver has begun a drive operation of the digital value.

28. The method of claim 21 , wherein said conditionally shutting off power to an I/O driver comprises conditionally shutting off power to the I/O driver after the I/O driver has begun a drive operation and before the I/O driver has completed the drive operation.

29. The system of claim 13 , wherein the detector is disposed on either the digital memory bank or the controller.