Composite device having three output terminals

1. A composite device comprising

a depletion mode FET including gate, drain and source terminals, and

an array of n bipolar transistors including

(n−1) bipolar transistors connected in parallel having respective first collector terminals tied together, and respective first emitter terminals tied together, and

one (1) sense bipolar transistor connected in parallel with the (n−1) bipolar transistors having a second collector terminal tied to the respective first collector terminals, and a second emitter terminal electrically isolated from the first emitter terminals,

wherein a voltage V CE between the first and second collector terminals and the first and second emitter terminals is configured to bias the depletion mode FET, and

a current I SENSE flowing through the second emitter terminal provides a value that is approximately equal to a current I D flowing through the drain terminal divided by (C*n), where C is a constant value and n is the size of the array.

2. The composite device of claim 1 wherein

the base terminals of the array of n bipolar transistors are connected together.

3. The composite device of claim 1 wherein

the array of n bipolar transistors includes n physically identical transistors.

4. The composite device of claim 1 wherein

each of the n bipolar transistors is matched in size to another of the n bipolar transistors by a predetermined proportionality factor.

5. The composite device of claim 1 wherein

the current I D flowing through the drain terminal is substantially equal to a sum of currents flowing through each of the first and second emitter terminals.

6. The composite device of claim 1 wherein

n is an integer value between 5 and 20.

7. The composite device of claim 1 wherein

the array of n bipolar transistors are replaced by an array of n NMOS transistors.

8. The composite device of claim 1 wherein

the gate terminal and the first emitter terminals are connected to ground to provide a high reverse isolation between the drain terminal and the array of n bipolar transistors.

9. A cascode device comprising:

a gallium nitride (GaN) transistor;

a silicon germanium (SiGe) bipolar transistor having collector and emitter terminals, respectively, connected to source and gate terminals of the GaN transistor;

a drain terminal of the GaN transistor for coupling to a load, in which the load is configured for connection to a relatively high voltage supply; and

a base terminal of the SiGe bipolar transistor for coupling to data, in which the data is configured to vary between voltages less than 2 volts;

wherein the SiGe bipolar transistor is a first transistor, and

the device further includes:

a plurality of SiGe bipolar transistors connected in parallel with the first SiGe bipolar transistor;

wherein each emitter terminal of the plurality of SiGe bipolar transistors is connected to the emitter terminal of the first SiGe bipolar transistor, and

each base terminal of the plurality of SiGe bipolar transistors is connected to the base terminal of the first SiGe bipolar transistor.

10. The cascode device of claim 9 wherein

the GaN transistor is a depletion mode field-effect-transistor, and

the gate terminal of the GaN transistor connected to a ground reference.

11. The cascode device of claim 9 wherein

the SiGe bipolar transistor is replaced by an n-channel metal-oxide-semiconductor (NMOS) field-effect-transistor (FET); and

the collector and emitter terminals of the SiGe transistor, respectively, are replaced by drain and source terminals of the NMOS FET.

12. The cascode device of claim 9 including

a second SiGe bipolar transistor connected in parallel with the first SiGe bipolar transistor;

a base terminal of the second SiGe bipolar transistor connected to the base terminal of the first SiGe bipolar transistor, and

an emitter terminal of the second SiGe bipolar transistor connected to an output terminal for sensing current flowing in the GaN transistor.

13. The cascade device of claim 9 wherein

The SiGe bipolar transistor is replaced by a silicon bipolar transistor.