Baseband phase-locked loop
View Patent ↗An example method includes receiving a phase correction signal representing a phase difference between a source signal and a reference signal, generating a first control voltage from the phase correction signal using a charge pump circuit, generating a second control voltage from the phase correction signal in response to a digitally filtered version of the phase correction signal, wherein the second control voltage corrects for an offset error present in the first control voltage, calculating a VCO control signal based on a linear combination of the first and the second control voltages; and generating the source signal in response to the VCO control signal.
1. A method comprising:
receiving a first phase correction signal representing a phase difference between a source signal and a reference signal;
generating a first control voltage from the first phase correction signal using a charge pump circuit;
generating a third control voltage, the combination of the first control voltage and the third control voltage including an offset error component due to time interval imbalances of the third control voltage;
generating a second control voltage from the first phase correction signal in response to a digitally filtered version of the phase correction signal, wherein the second control voltage corrects for the offset error by balancing the time interval imbalances, wherein the first control voltage is generated in parallel with the second control voltage from the first phase correction signal;
calculating a VCO control signal based on a linear combination of the first control voltage, the third control voltage, and the second control voltage by summing the first control voltage, the third control voltage, and the second control voltage; and
generating the source signal in response to the VCO control signal.
2. The method of claim 1 , wherein the second control voltage is generated by a digital-to-analog converter (DAC) in response to the digitally filtered version of the first phase correction signal.
3. The method of claim 1 , wherein the first phase correction signal is a binary signal that controls charging and discharging of the charge pump circuit.
4. The method of claim 1 , wherein the linear combination of the first and second voltages is formed by a signal summer.
5. The method of claim 1 , wherein the source signal is a data signal having signal level transitions.
6. The method of claim 1 , wherein the digitally filtered version of the first phase correction signal is generated by a digital filter having an infinite impulse response.
7. The method of claim 1 , wherein the third control voltage is generated by a direct update circuit having a predetermined gain factor.
8. An apparatus comprising:
a direct update circuit generating a third control voltage in response to a first phase correction signal, the third control voltage including positive pulses and negative pulses;
a charge pump circuit generating a first control voltage in response to the first phase correction signal, the combination of the first control voltage and the third control voltage including an error signal produced by imbalanced time intervals of the positive pulses and the negative pulses;
a compensation circuit generating a second control voltage in response to the first phase correction signal which balances the time interval imbalances of the positive pulses and the negative pulses, wherein the apparatus is configured such that the charge pump circuit and compensation circuit generate the first control voltage and the second control voltage in response to the same first phase correction signal in parallel;
a signal summer summing the first control voltage, the second control voltage, and the third control voltage and generating a VCO control signal based on a linear combination of the first control voltage, the second control voltage, and the third control signal; and
a voltage controlled oscillator generating a clock signal in response to the VCO control signal.
9. The apparatus of claim 8 , further comprising a decision circuit for generating the first phase correction signal in response to a phase difference between a reference signal and the clock signal.
10. The apparatus of claim 8 , wherein the compensation circuit further comprises a digital filter for generating a digitally filtered signal in response to the first phase correction signal.
11. The apparatus of claim 10 , wherein the compensation circuit further comprises a digital-to-analog converter (DAC) for generating the second control voltage in response to the digitally filtered signal.
12. The apparatus of claim 10 , wherein the digital filter has an infinite impulse response.
13. The apparatus of claim 8 , wherein the direct update circuit comprises a high-bandwidth amplifier having a predetermined gain factor in a range of about 0.005 to about 0.015.
14. The apparatus of claim 8 , wherein the compensation circuit comprises:
a digital filter having an infinite impulse response for generating a digitally filtered signal in response to the first phase correction signal; and
a digital-to-analog converter (DAC) for generating the second control voltage in response to the digitally filtered signal,
wherein parameters of the digital filter are selected depending on the charge pump circuit.
15. The apparatus of claim 14 , wherein the digital filter includes a plurality of zero points selected to cancel the pole points of the charge pump circuit.
16. The apparatus of claim 8 , wherein the direct update circuit comprises a high-bandwidth amplifier.
17. A method comprising:
generating a VCO control signal to correct a phase error in response to a phase error signal, wherein the VCO control signal is generated by summing a charge pump signal and a digital filter component signal to form a linear combination thereof, wherein the VCO control signal includes:
positive pulses and negative pulses generated by a direct update circuit;
the charge pump signal generated by a charge pump circuit in response to the phase error signal, wherein the combination of the charge pump signal and the positive pulses and the negative pulses includes an error component produced by imbalanced time intervals of the positive pulses and the negative pulses; and
the digital filter component signal generated in response to the phase error signal by a digital filter and a digital-to-analog converter, wherein the digital filter component signal acts to offset the error component by balancing the imbalanced time intervals of the positive pulses and the negative pulses.
18. The method of claim 17 , wherein the digital filter has an infinite impulse response.
19. The method of claim 17 , wherein the phase error signal is generated by a decision circuit from a reference signal and a VCO output signal and the phase error is a difference between the reference signal and the VCO output signal.
20. The method of claim 17 , wherein the phase error signal is a binary signal that controls the charging and discharging of the charge pump circuit.