IP Library Granted Patent US 8,390,045
Granted Patent B2
US 8,390,045 · App. 12/547,126 · Granted Mar 5, 2013

Semiconductor device and method of manufacturing same

Inventor: Wensheng Wang (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,390,045
App. No.
12/547,126
Granted
Mar 5, 2013
Kind
B2
Abstract

A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx 1 and whose actual composition is expressed as AOx 2 ; a second layer formed on the first layer and formed of an oxide whose stoichiometric composition is expressed as BOy 1 and whose actual composition is expressed as BOy 2 ; and a metal layer formed on the second layer. The second layer is higher in ratio of oxidation than the first layer. The composition parameters x 1 , x 2 , y 1 , and y 2 satisfy y 2 /y 1 >x 2 /x 1 , and the second layer includes an interface layer of the stoichiometric composition formed at an interface with the metal layer. The interface layer is higher in ratio of oxidation than the rest of the second layer.

Claims (26)

1. A semiconductor device, comprising:

a substrate; and

a ferroelectric capacitor formed on the substrate, the ferroelectric capacitor including

a lower electrode;

a ferroelectric film formed on the lower electrode; and

an upper electrode formed on the ferroelectric film, the upper electrode including

a first layer formed of an oxide whose stoichiometric composition is expressed as chemical formula AOx 1 using a composition parameter x 1 and whose actual composition is expressed as chemical formula AOx 2 using a composition parameter x 2 ;

a second layer formed on the first layer, the second layer being formed of an oxide whose stoichiometric composition is expressed as chemical formula BOy 1 using a composition parameter y 1 and whose actual composition is expressed as chemical formula BOy z using a composition parameter y 2 ; and

a metal layer formed on the second layer,

wherein the second layer is higher in ratio of oxidation than the first layer,

the composition parameters x 1 , x 2 , y 1 , and y 2 satisfy y 2 /y 1 >x 2 /x 1 , and

the second layer includes a first region of the stoichiometric composition formed at an interface with the metal layer and a second region between the first region and the first layer, and an oxygen concentration of the second layer is higher in the first region than in the second region.

2. The semiconductor device as claimed in claim 1 , wherein a metal element of the first layer is equal to a metal element of the second layer.

3. The semiconductor device as claimed in claim 1 , wherein the first and second layers are formed of an iridium oxide.

4. The semiconductor device as claimed in claim 1 , wherein a metal element of the first layer is different from a metal element of the second layer.

5. The semiconductor device as claimed in claim 1 , wherein an interface between the ferroelectric film and the first layer is flat.

6. The semiconductor device as claimed in claim 1 , wherein the first layer includes Pb and the second layer is substantially free of Pb.

7. The semiconductor device as claimed in claim 1 , further comprising:

an insulating film covering the ferroelectric capacitor; and

an interconnection structure formed on the insulating film,

wherein the metal layer is connected to an interconnection pattern in the interconnection structure through a contact hole.

8. The semiconductor device as claimed in claim 1 , wherein:

the second layer consists of the oxide whose stoichiometric composition is expressed as chemical formula BOy 1 and whose actual composition is expressed as chemical formula BOy 2 , and

the first region and the second region of the second layer are in direct contact with each other.

9. The semiconductor device as claimed in claim 1 , wherein the second layer is crystallized.

10. The semiconductor device as claimed in claim 6 , wherein the upper electrode includes a flat interface between the second layer and the metal layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2009
From: WANG, WENSHENG
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023145/0776 →
Continuity (2)
Continuation PCTJP2007055694 · Mar 20, 2007
Related Publication 20090309188A1 · Dec 17, 2009