Granted Patent B2

US 9,001,846 · App. 12/550,004 · Granted Apr 7, 2015

Abstract

Claims (44)

1. An apparatus comprising:

a media-side physical layer (PHY) block configured to receive a received signal via at least one medium, decode the received signal into data, and send the data to a media-side medium access control (MAC) block;

the media-side MAC block configured to receive the data from the media-side PHY layer block, determine a time of receipt of the data, and send the data and a control time to a system-side MAC block;

the system-side MAC block configured to receive the data and the control time from the media-side MAC block and send the data to a system-side PHY block after a predetermined delay after the time of receipt of the data based on the control time, the predetermined delay being programmable to accommodate different flow control functions performed by the apparatus;

the system-side PHY block configured to receive the data from the system-side MAC block, encode the data into a transmitted signal, and transmit the transmitted signal to a computing system; and

a low power policy engine configured to control whether the media-side PHY block is in a low power state based on idle statistics received from the system-side MAC block.

2. The apparatus of claim 1 , wherein the media-side PHY block includes:

a media-side physical medium attachment (PMA) block configured to receive the received signal via the at least one medium and send the received signal to a media-side physical coding sublayer (PCS) block; and

the media-side PCS block configured to decode the received signal into the data and send the data to the media-side MAC block.

3. The apparatus of claim 2 , wherein the system-side PHY block includes:

a system-side PCS block configured to receive the data from the system-side MAC block, encode the data into the transmitted signal, and send the transmitted signal to a system-side PCS block; and

the system-side PCS block configured to receive the transmitted signal from the system-side PCS block and transmit the transmitted signal to the computing system.

4. The apparatus of claim 1 , wherein the system-side MAC block is configured to receive the data and a control signal from the media-side MAC block and send the data to a system-side PHY block after the predetermined delay after receiving the data based on the control signal.

5. The apparatus of claim 1 , wherein the media-side MAC block is configured to perform carrier sense multiple access with collision detection (CSMA-CD) functions on the data.

6. The apparatus of claim 1 , wherein the media-side MAC block is configured to encrypt the data, and the system-side MAC block is configured to decrypt the data.

7. The apparatus of claim 1 , wherein the system-side MAC block includes a buffer configured to store the data until the predetermined delay after receiving the data.

8. The apparatus of claim 1 , wherein the media-side MAC block includes a priority flow controller (PFC) configured to determine which of the data include flow-control information and send the data which include flow control information to the system-side MAC block before sending data which do not include flow control information to the system-side MAC block.

9. The apparatus of claim 1 , wherein:

the media-side MAC block includes a link fault detector configured to recognize a mediaside link fault signal received from the media-side PHY block and, in response to recognizing the media-side link fault signal, assert a MAC-level link fault signal to the system-side MAC block, and

the system-side MAC block includes a link fault generator configured to generate and send a system-side link fault signal to the system-side PHY block in response to receiving the MAC-level link fault signal.

10. The apparatus of claim 1 , wherein:

the media-side physical layer (PHY) block is programmable for different coding schemes; and

the predetermined delay is based on the programmed coding scheme.

11. The apparatus of claim 1 , wherein the media-side MAC block is configured to send, to the system-side MAC block, a time at which the system-side MAC block should send the data to the system-side PHY block.

12. An apparatus comprising:

a media-side physical layer (PHY) block configured to receive a received signal via at least one medium, decode the received signal into data, and send the data to a media-side medium access control (MAC) block;

the media-side MAC block configured to receive the data from the media-side PHY layer block, determine a time of receipt of the data, and send the data and a control time to a system-side MAC block;

the system-side MAC block configured to receive the data and the control time from the media-side MAC block and send the data to a system-side PHY block after a predetermined delay after the time of receipt of the data based on the control time, the predetermined delay being programmable to accommodate different flow control functions performed by the apparatus;

the system-side PHY block configured to receive the data from the system-side MAC block, encode the data into a transmitted signal, and transmit the transmitted signal to a computing system; and

a low power policy engine configured to control whether the media-side PHY block is in a low power state based on a number of packets stored in a buffer which stores packets transmitted between the media-side MAC block and the system-side MAC block.

13. An apparatus comprising:

a media-side physical layer (PHY) block configured to receive a received signal via at least one medium, decode the received signal into data, and send the data to a media-side medium access control (MAC) block;

the media-side MAC block configured to receive the data from the media-side PHY layer block, determine a time of receipt of the data, and send the data and a control time to a system-side MAC block;

the system-side MAC block configured to receive the data and the control time from the media-side MAC block and send the data to a system-side PHY block after a predetermined delay after the time of receipt of the data based on the control time, the predetermined delay being programmable to accommodate different flow control functions performed by the apparatus;

the system-side PHY block configured to receive the data from the system-side MAC block, encode the data into a transmitted signal, and transmit the transmitted signal to a computing system; and

a low power policy engine configured to control whether the media-side PHY block is in a low power state based on a type of at least one packet destined for the media-side MAC block.

14. The apparatus of claim 13 , wherein:

the media-side physical layer (PHY) block is programmable for different coding schemes; and

the predetermined delay is based on the programmed coding scheme.

15. The apparatus of claim 13 , wherein the media-side MAC block is configured to send, to the system-side MAC block, a time at which the system-side MAC block should send the data to the system-side PHY block.

16. The apparatus of claim 13 , wherein the system-side MAC block is configured to receive the data and a control signal from the media-side MAC block and send the data to a system-side PHY block after the predetermined delay after receiving the data based on the control signal.

17. The apparatus of claim 13 , wherein:

the media-side MAC block includes a link fault detector configured to recognize a mediaside link fault signal received from the media-side PHY block and, in response to recognizing the media-side link fault signal, assert a MAC-level link fault signal to the system-side MAC block, and

the system-side MAC block includes a link fault generator configured to generate and send a system-side link fault signal to the system-side PHY block in response to receiving the MAC-level link fault signal.

Assignments (7)