Thermometer code transcoding and encoding methods and systems

1. An error suppression circuit apparatus for generating an output signal having an output code from an input signal having a thermometer code representation, the error suppression circuit apparatus comprising:

a clustering circuit block configured to accept input code bits of the thermometer code representation of the input signal and to partition the input code bits into non-overlapping clusters, wherein each of the clusters comprises a portion of the input code bits;

a control signal generation circuit block configured to generate a control signal for each of the clusters based on, at least in part, a logical OR operation over all bits in a corresponding one of the clusters;

a cluster selection circuit block configured to determine a transition cluster for the input code bits based on, at least in part, the control signals, the transition cluster comprising a 1/0 transition in the input code bits, the cluster selection circuit block configured to determine one or more bits of the output code based on, at least in part, an identity of the transition cluster; and

an encoding circuit block configured to determine the remaining bits of the output code based on, at least in part, an input code bit pattern in the transition cluster, the remaining bits having lower significant bit positions in the output code than the one or more bits,

wherein the number of bits in the output code is less than the number of bits in the input code bits, and the total number of bits in the clusters is the same as the number of bits in the input code bits,

wherein the control signal generation circuit block and the encoding circuit block are configured to operate without performing an XOR operation.

2. The error suppression circuit apparatus of claim 1 , wherein the thermometer code comprises a sign bit and a plurality of magnitude bits.

3. The error suppression circuit apparatus of claim 1 , wherein K=2 M , wherein K is the number of bits in the input code bits plus one, and M is the number of bits in the output code.

4. The error suppression circuit apparatus of claim 1 , wherein a first one of the clusters is configured to contain N−1 number of bits and is configured to contain lowest significant bits of the input code bits, each of the remaining ones of the clusters is configured to contain N number of bits, and K=L*N, and

wherein K is the number of bits in the input code bits plus one, L is the number of the clusters, and N is a positive integer.

5. The error suppression circuit apparatus of claim 1 , wherein a first one of the clusters is configured to contain less number of bits than a second one of the clusters if the first one of the clusters is configured to contain lower significant bits of the input code bits, as compared to the second one of the clusters.

6. The error suppression circuit apparatus of claim 1 , wherein the control signal generation circuit block comprises a plurality of bipolar junction transistors (BJTs) in an emitter-coupled configuration.

7. A flash analog-to-digital conversion (ADC) circuit comprising the error suppression circuit apparatus of claim 1 and an input signal processing circuit, wherein the input signal processing circuit is configured to receive an analog signal input, wherein the input signal is a thermometer code representation of the analog signal input, wherein the input signal represents the analog signal input with bubble errors.

8. An error suppression method for generating an output signal having an output code from an input signal having a thermometer code representation utilizing circuits, the method comprising:

partitioning, using a circuit, input code bits of the thermometer code representation of the input signal into non-overlapping clusters, wherein each of the clusters comprises a portion of the input code bits;

identifying, using a circuit, a transition cluster for the input code bits based on, at least in part, a logical OR operation over all bits in a cluster, the transition cluster comprising a 1/0 transition in the input code bits;

determining, using a circuit, one or more bits of the output code based on, at least in part, an identity of the transition cluster;

determining, using a circuit, the remaining bits of the output code based on, at least in part, an input code bit pattern in the transition cluster, the remaining bits having lower significant bit positions in the output code than the one or more bits,

wherein the number of bits in the output code is less than the number of bits in the input code bits, and the total number of bits in the clusters is the same as the number of bits in the input code bits,

wherein the identifying the transition cluster and the determining the remaining bits are performed without an XOR operation.

9. The error suppression method of claim 8 , wherein the thermometer code comprises a sign bit and a plurality of magnitude bits.

10. The error suppression method of claim 8 , wherein K=2 M , wherein K is the number of bits in the input code bits plus one, and M is the number of bits in the output code.

11. The error suppression method of claim 8 , wherein a first one of the clusters is configured to contain N−1 number of bits and is configured to contain lowest significant bits of the input code bits, each of the remaining ones of the clusters is configured to contain N number of bits, and K=L*N, and

wherein K is the number of bits in the input code bits plus one, L is the number of the clusters, and N is a positive integer.

12. The error suppression method of claim 8 , wherein a first one of the clusters is configured to contain less number of bits than a second one of the clusters if the first one of the clusters is configured to contain lower significant bits of the input code bits, as compared to the second one of the clusters.

13. The error suppression method of claim 8 , wherein the identifying operation is performed using, at least in part, a plurality of bipolar junction transistors (BJTs) in an emitter-coupled configuration.

14. The error suppression method of claim 8 , wherein the determining the remaining bits of the output code comprises performing, based on the one or more bits of the output code, a carryover calculation.

15. An error suppression circuit apparatus for generating an output signal having an output code from an input signal having a thermometer code representation, comprising:

means for accepting input code bits of the thermometer code representation of the input signal and partitioning the input code bits into non-overlapping clusters, wherein each of the clusters comprises a portion of the input code bits;

means for identifying a transition cluster for the input code bits based on, at least in part, a logical OR operation over all bits in a cluster, the transition cluster comprising a 1/0 transition in the input code bits;

means for determining one or more bits of the output code based on, at least in part, an identity of the transition cluster; and

means for determining the remaining bits of the output code based on, at least in part, an input code bit pattern in the transition cluster, the remaining bits having lower significant bit positions in the output code than the one or more bits,

wherein the number of bits in the output code is less than the number of bits in the input code bits, and the total number of bits in the clusters is the same as the number of bits in the input code bits,

wherein the means for identifying the transition cluster and the means for determining the remaining bits are configured to operate without performing an XOR operation.

16. The error suppression circuit apparatus of claim 15 , wherein the thermometer code comprises a sign bit and a plurality of magnitude bits.

17. The error suppression circuit apparatus of claim 15 , wherein K=2 M , wherein K is the number of bits in the input code bits plus one, and M is the number of bits in the output code.

18. The error suppression circuit apparatus of claim 15 , wherein a first one of the clusters is configured to contain N−1 number of bits and is configured to contain lowest significant bits of the input code bits, each of the remaining ones of the clusters is configured to contain N number of bits, and K=L*N, and

wherein K is the number of bits in the input code bits plus one, L is the number of the clusters, and N is a positive integer.

19. The error suppression circuit apparatus of claim 15 , wherein a first one of the clusters is configured to contain less number of bits than a second one of the clusters if the first one of the clusters is configured to contain lower significant bits of the input code bits, as compared to the second one of the clusters.