IP Library Granted Patent US 8,211,809
Granted Patent B2
US 8,211,809 · App. 12/551,846 · Granted Jul 3, 2012

Method of producing semiconductor device

Assignee: Unisantis Electronics Singapore Pte Ltd.
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Quick Facts
Patent No.
US 8,211,809
App. No.
12/551,846
Granted
Jul 3, 2012
Kind
B2
Abstract

It is intended to produce a semiconductor device with a stable gate length, using an end-point detection process based on monitoring a plasma emission intensity during dry etching for setting a gate length. A semiconductor device production method of the present invention comprises the steps of: forming a first dielectric or gate conductive film to allow a pillar-shaped semiconductor layer to be buried therein; flattening the first dielectric or gate conductive film while detecting an end-point using a stopper formed on top of the pillar-shaped semiconductor layer; forming a second dielectric or gate conductive film; etching the second dielectric or gate conductive film and calculating an etching rate during the etching; and detecting an end-point of etching of the first dielectric or gate conductive film, based on the etching rate of the second dielectric or gate conductive film during etching-back of the second dielectric or gate conductive film, to control an etching amount of the first dielectric or gate conductive film.

Claims (25)

1. A method of producing a semiconductor device in which at least one pillar-shaped semiconductor layer is provided on a semiconductor substrate, and a dielectric film is provided on respective surfaces of the semiconductor substrate and the at least one pillar-shaped semiconductor layer, the method comprising:

(a) forming a first gate conductive film to cover respective surfaces of the at least one pillar-shaped semiconductor layer and a hard mask formed on a top of the at least one pillar-shaped semiconductor layer;

(b) after step (a), flattening an upper surface of the first gate conductive film, using the hard mask as a stopper;

(c) after step (b), forming a second gate conductive film on the flattened surface of the first gate conductive film;

(d) after step (c), anisotropically etching the second gate conductive film;

(e) monitoring an intensity of plasma emission emitted from the second gate conductive film during the etching to detect an end-point at which the etching of the second gate conductive film needs to end, based on a change in the plasma emission intensity;

(f) after step (e), anisotropically etching the first gate conductive film; and

(g) determining an end-point at which the etching of the first gate conductive film needs to end, using an etching rate of the first gate conductive film determined with a relative ratio between the etching rate of the first gate conductive film and an etching rate of the second gate conductive film calculated from a film thickness of the second gate conductive film and a time taken from a beginning to an end of the etching of the second gate conductive film.

2. The method as defined in claim 1 , wherein each of the first gate conductive film and the second gate conductive film is made of polysilicon.

3. The method as defined in claim 1 , wherein the first gate conductive film and the second gate conductive film are made of a same metal material.

4. The method as defined in claim 1 , wherein the first gate conductive film and the second gate conductive film are made of different metal materials, respectively.

5. The method as defined in claim 1 , wherein the semiconductor substrate comprises a diffusion area formed at a lower surface of a respective of the at least one pillar-shaped semiconductor layer, and the method further comprises:

after step (f), patterning the first gate conductive film on a sidewall of the at least one pillar-shaped semiconductor layer to form a gate electrode; and

(j) after step (i), forming, on an upper surface of a respective of the at least one pillar-shaped semiconductor layer, a diffusion area having the same conductive type as that of the diffusion area formed at the lower surface of a respective of the at least one pillar-shaped semiconductor layer.

6. A method of producing a semiconductor device in which at least one pillar-shaped semiconductor layer is provided on a semiconductor substrate, the method comprising:

(a) forming a first dielectric film to cover respective surfaces of the at least one pillar-shaped semiconductor layer and a hard mask formed on a top of the at least one pillar-shaped semiconductor layer;

(b) after step (a), flattening an upper surface of the first dielectric film, using the hard mask as a stopper;

after step (b), forming a second dielectric film on the flattened surface of the first dielectric film;

(d) after step (c), anisotropically etching the second dielectric film;

(e) monitoring an intensity of plasma emission emitted from the second dielectric film during the etching to detect an end-point at which the etching of the second dielectric film needs to end, based on a change in the plasma emission intensity;

after step (e), anisotropically etching the first dielectric film;

(g) after step (f), forming a gate electrode extensive over an upper surface of the first dielectric film and a sidewall of the at least one pillar-shaped semiconductor layer; and

(h) determining an end-point at which the etching of the first dielectric film needs to end, using an etching rate of the first dielectric film determined with a relative ratio between the etching rate of the first dielectric film and an etching rate of the second dielectric film calculated from a film thickness of the second dielectric film and a time taken from a beginning to an end of the etching of the second dielectric film.

7. The method as defined in claim 6 , wherein each of the first dielectric film and the second dielectric film is made of a silicon oxide.

8. The method as defined in claim 6 , wherein the semiconductor substrate comprises a diffusion area formed at a lower surface of a respective of the at least one pillar-shaped semiconductor layer, and the method further comprises, after step (g), forming, on an upper surface of a respective of the at least one pillar-shaped semiconductor layer, a diffusion area having the same conductive type as that of the diffusion area formed at the lower surface of a respective of the at least one pillar-shaped semiconductor layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2011
From: UNISANTIS ELECTRONICS JAPAN LTD.
To: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.
Reel/Frame 026970/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2009
From: MASUOKA, FUJIO; ARAI, SHINTARO
To: UNISANTIS ELECTRONICS (JAPAN) LTD.
Reel/Frame 023327/0033 →
Priority Claims (1)
JP PCT/JP2008/065718 · Sep 2, 2008 · national
Continuity (2)
Provisional Application 61207635 · Feb 13, 2009
Related Publication 20100087017A1 · Apr 8, 2010