Granted Patent B2

US 8,315,272 · App. 12/552,240 · Granted Nov 20, 2012

Abstract

Claims (47)

1. A multilane to single lane digital interface translator, comprising:

multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard using a coding scheme;

an auxiliary channel input configured to receive an auxiliary data channel; and

a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard;

wherein the multilane to single lane digital interface translator is configured to encode the received data to produce code groups, where the same type of code group is on each lane at any given time, and the type of the code group is determined by the coding scheme used to encode the received data;

wherein the multilane to single late digital interface translator is configured to interleave the code groups by mapping the code groups to packets, where each packet includes a specific type of code group;

wherein the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate; and

wherein the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard.

2. The digital interface translator of claim 1 , wherein the multiple receiver lanes are configurable to decode data channels encoded in accordance with one of a plurality of digital interface standards.

3. The digital interface translator of claim 1 , wherein the output digital interface standard is the 10 Gigabit IEEE 802.3 Clause 49 standard.

4. The digital interface translator of claim 1 , wherein the input digital interface standard is the Display Port standard.

5. The digital interface translator of claim 4 , wherein the digital interface translator is configured to utilize the following definitions:

∥C∥=K 0 x.y/K 2 x.y/K 2 x.y/K 3 x.y/

∥D∥=D 0 x.y/D 1 x.y/D 2 x.y/D 3 x.y/

∥S dp ∥=/S/D0.0/D0.0/D0.0/

∥T 0 ∥=/T/I/I/I/, defined in IEEE 802.3 Clause 48

∥I∥=/I/I/I/I/, defined in IEEE 802.3 Clause 48

to map decoded data code groups Dx.y and decoded special code groups Kx.y to XGMII according to the following rules:

insert ∥S dp ∥ in between ∥C∥ and ∥D∥;

insert ∥T 0 ∥, ∥I∥ in between ∥D∥ and ∥C∥;

pass ∥C∥ through without modification;

insert ∥T 0 ∥, ∥I∥, . . . , ∥I∥, ∥S dp ∥ in a sequence of ∥D∥ to rate match to the output digital interface standard; and

insert ∥I∥ in a sequence of ∥C∥ to rate match to the output digital interface standard.

6. The digital interface translator of claim 5 , wherein the digital interface translator is configured to replace ∥I∥ columns with auxiliary data received via the auxiliary channel.

7. The digital interface translator of claim 1 , wherein the input digital interface standard is the HDMI standard.

8. The digital interface translator of claim 7 , wherein the digital interface translator is configured to utilize the following definitions:

∥C 0 ∥=/K 2 x.y/I/I/I/

∥C 1 ∥=/K 1 x.y/K 2 x.y/I/I/

∥C 2 ∥=/K 0 x.y/K 1 x.y/K 2 x.y/I/

∥C 3 ∥=/K 0 x.y/K 1 x.y/K 2 x.y/K 0 x.y/K 1 x.y/K 2 x.y/K 0 x.y/K 1 x.y/, /K 2 x.y/K 0 x.y/K 1 x.y/K 2 x.y/

∥D∥=/D 0 x.y/D 1 x.y/D 2 x.y/D 0 x.y/, /D 1 x.y/D 2 x.y/D 0 x.y/D 1 x.y/, /D 2 x.y/D 0 x.y/D 1 x.y/D 2 x.y/

|S hv ∥=/S/D0.0/D0.0/D0.1/, SOP for VDC data

∥S ht ∥=/S/D0.0/D0.0/D1.1/, SOP for Data Island TERC4 data

∥T 0 ∥=/T/I/I/I/, defined in IEEE 802.3 Clause 48

∥I∥=/I/I/I/I/, defined in IEEE 802.3 Clause 48

to map decoded data code groups Dx.y and decoded special code groups Kx.y to XGMII according to the following rules:

insert ∥S hv ∥ in between ∥C n ∥ and ∥D∥ where ∥D∥ is VDC data;

insert ∥S ht ∥ in between ∥C n ∥ and ∥D∥ where ∥D∥ is TERC4 data;

following any ∥S∥, the 1 st ∥D∥=/D0/D1/D2/D0/, the 2 nd ∥D∥=/D1/D2/D0/D1/, and the 3 rd ∥D∥=/D2/D0/D1/D2/, etc.;

insert ∥T n ∥, ∥I∥ in between ∥D∥ and ∥C∥, ∥T 1 ∥=/D2/T/I/I/, ∥T 2 ∥=/D1/D2/T/I/, ∥T 3 ∥=/D0/D1/D2/T/;

after a ∥T n ∥ or ∥I∥, the 1st ∥C∥=/C0/C1/C2/C0/, the 2nd ∥C∥=/C1/C2/C0/C1/, and the 3rd ∥C∥=/C2/C0/C1/C2/, etc.;

the last ∥C∥ before an ∥I∥, ∥S hv ∥ or ∥S ht ∥ is padded with /I/ code groups, ∥C∥=/C0/C1/C2/I/, /C1/C2/I/I/, or /C2/I/I/I/;

insert ∥T∥, ∥I∥, . . . , ∥I∥, ∥S hv ∥ or ∥S ht ∥ as appropriate in a sequence of ∥D∥columns to rate match to 10.3125 GBaud;

insert ∥Tn∥, ∥I∥, . . . , ∥I∥, ∥S hv ∥ or ∥S ht ∥ as appropriate in a sequence of ∥D∥ columns to rate match to 10.3125 GBd; and

insert ∥I∥ in a sequence of ∥C∥ to rate match to the output digital interface standard.

9. The digital interface translator of claim 8 , wherein the digital interface translator is configured to replace ∥I∥ columns with auxiliary data received via the auxiliary channel.

10. The digital interface translator of claim 1 , wherein the input digital interface standard is the DVI standard.

Assignments (8)