Noise-shaped scrambler for reduced out-of-band common-mode interference
View Patent ↗Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.
1. A circuit comprising:
a common mode scrambler circuit comprising:
a p input receiving a p input signal and an n input receiving an n input signal, wherein the p input signal and the n input signal is either in a low state or a high state;
a p output transmitting a p output signal and an n output transmitting an n output signal, wherein the p output signal and the n output signal is either in a low state or a high state; and
scrambler logic circuitry configured to receive a scrambler control signal which is either in a low state or a high state,
wherein when the p input signal and the n input signal are in different states, the scrambler logic circuitry causes the p output signal to be in the same state as the p input signal and causing the n output signal to be in the same state as the n input signal, and
wherein when the p input signal and the n input signal are in the same state, the scrambler logic circuitry generates the p output signal and the n output signal as a function of at least the scrambler control signal.
2. The circuit of claim 1 wherein when the p input signal and the n input signal are in the same state, the scrambler logic circuitry causes the p output signal to be in the high state and the n output signal to be in the high state when the scrambler control signal is in the high state and causes the p output signal to be in the low state and the n output signal to be in the low state when the scrambler control signal is in the low state.
3. The circuit of claim 1 wherein when the p input signal and the n input signal are in the same state, the scrambler logic circuitry causes the p output signal to be in the same state as the p input signal and the n output signal to be in the same state as the n input signal when the scrambler control signal is in the low sate and causes the p output signal to be in the inverse state of the p input signal and the n output signal to be in the inverse state of the n input signal when the scrambler control signal is in the high state.
4. The circuit of claim 1 further comprising:
a 3-level PWM generator having a PWM p output and a PWM n output;
a first half bridge circuit driven by the p output signal; and
a second half bridge circuit driven by the n output signal, wherein the p input signal is received from the PWM p output and the n input signal is received from the PWM n output.
5. The circuit of claim 1 , further comprising a noise shaping circuit configured to send the scrambler control signal to the common-mode scrambler circuit.
6. The circuit of claim 5 , wherein the noise shaping circuit comprises a delta-sigma modulator.
7. The circuit of claim 6 , wherein the delta-sigma modulator is a k th -order delta-sigma modulator, where k is greater than 4.
8. The circuit of claim 1 further comprising:
a first buffer between the common-mode scrambling circuit and the first half-bridge circuit and
a second buffer between the common-mode scrambling circuit and the second half-bridge circuit.
9. The circuit of claim 1 further comprising:
a low pass filter.
10. A method for scrambling outputs of a three-level PWM generator comprising:
receiving a PWM p signal and a PWM n signal from the three-level PWM generator, wherein the PWM p signal and the PWM n signal is either in a low state or a high state;
receiving a scrambler control signal which is either in a low state or a high state;
generating a p output signal and an n output signal;
wherein when the PWM p signal and the PWM n signal are in different states, the p output signal is set to the same state as the PWM p signal and the n output signal is set to the same state as the PWM n signal, and
wherein when the PWM p signal and the PWM n signal are in the same state, the p output signal and the n output signal are a function of at least the scrambler control signal.
11. The method of claim 10 wherein when the PWM p signal and the PWM n signal are in the same state, the p output signal and the n output signal are both set to the same state as the scrambler control signal.
12. The method of claim 10 wherein when the PWM p signal and the PWM n signal are in the same state, the p output signal and the n output signal are set to the same state as the PWM p signal when the scrambler control signal is in the low state, and the p output signal and the n output signal are set to the inverse state of the PWM p signal when the scrambler control signal is in the high state.
13. The method of claim 10 , further comprising:
generating the scrambler control signal with a noise shaping circuit.
14. The method of claim 13 , wherein the noise shaping circuit comprises a delta-sigma modulator.
15. The method of claim 10 , further comprising
generating the PWM p signal and the PWM n signal by a three-level PWM generator;
driving a first half-bridge circuit by the p output signal;
driving a second half-bridge circuit by the n output signal.
16. A circuit comprising:
a common-mode scrambler circuit comprising:
a p input receiving a p input signal and an n input receiving an n input signal, wherein the p input signal and the n input signal is either in a low state or a high state;
a p output transmitting a p output signal and an n output transmitting an n output signal, wherein the p output signal and the n output signal is either in a low state or a high state; and
means for scrambling the p input signal and the n input signal to produce signals at the p output signal and n output signal;
wherein when the p input signal and the n input signal are in different states, the means for scrambling causes the p output signal to be in the same state as the p input signal and causes the n output signal to be in the same state as the n input signal, and
wherein when the p input signal and the n input signal are in the same state, the means for scrambling generates the p output signal and the n output signal as a function of at least the scrambler control signal.
17. The circuit of claim 16 wherein when the p input signal and the n input signal are in the same state, the means for scrambling causes the p output signal to be in the high state and the n output signal to be in the high state when the scrambler control signal is in the high state and causes the p output signal to be in the low state and the n output signal to be in the low state when the scrambler control signal is in the low state.
18. The circuit of claim 16 further comprising:
means for generating a first PWM signal for the p input;
means for generating a second PWM signal for the n input;
means for amplifying the p output; and
means for amplifying the n output.
19. The circuit of claim 16 , further comprising noise shaping means for generating the scrambler control signal.
20. The circuit of claim 16 , further comprising:
means for low pass filtering.