Switch circuit
View Patent ↗A switch circuit includes: a first charge/discharge circuit having a fixed first time constant; a second charge/discharge circuit having a second time constant associated with the operation statuses of a plurality of switches; first and second input/output ports to which the first and second charge/discharge circuits are connected, respectively; and a control section adapted to measure the first and second time constants by charging or discharging the first and second charge/discharge circuits and determine the operation statuses of a plurality of switches based on the ratio of the measured first and second time constants.
1. A switch circuit comprising:
a first charge/discharge circuit having a fixed first time constant;
a second charge/discharge circuit having a second time constant associated with operation statuses of a plurality of switches and including a plurality of resistors and the plurality of switches, each of the switches connected in parallel only with one of the plurality of resistors;
first and second general purpose input/output (GPIO) ports to which the first and second charge/discharge circuits are connected, respectively; and
a control section adapted to measure the first and second time constants by charging or discharging the first and second charge/discharge circuits and determine the operation statuses of the plurality of switches based on a ratio of the measured first and second time constants.
2. The switch circuit of claim 1 , wherein
the control section measures the first and second time constants via the first and second input/output ports.
3. The switch circuit of claim 1 , wherein
the control section includes a third input/output port and measures the first and second time constants via the third input/output port.
4. The switch circuit of claim 1 , wherein
the first charge/discharge circuit includes a reference resistor having a fixed resistance and a first capacitor,
the second charge/discharge circuit includes a series circuit having the plurality of resistors and a second capacitor, and
combined resistances of the plurality of resistors are in a one-to-one correspondence with the operation statuses of the plurality of switches.
5. The switch circuit of claim 4 , wherein
resistances of each of the plurality of resistors differ from each other and are each a power of 2.
6. The switch circuit of claim 4 , wherein
a single common capacitor is used as the first and second capacitors.
7. The switch circuit of claim 6 , wherein
an element adapted to form a discharge path of the common capacitor is connected in parallel with the reference resistor.
8. The switch circuit of claim 1 , wherein
the first charge/discharge circuit includes a reference capacitor having a fixed capacitance and a first resistor, and
the second charge/discharge circuit includes a plurality of capacitors, a plurality of switches which are each connected in series with one of the capacitors, and a second resistor.
9. The switch circuit according to claim 1 , wherein
a determined operation status of two or more of the plurality of switches is on.
10. The switch circuit according to claim 1 , wherein
the combined resistances of the plurality of resistors are in a one-to-one correspondence with every combination of operation statuses of the plurality of switches.
11. The switch circuit according to claim 1 , wherein
combinations of a switch and a resistor connected in parallel with the switch are connected in series with each other.
12. The switch circuit according to claim 1 , wherein
the control section measures the second time constant by determining a time period between when the second charge/discharge circuit begins to charge or discharge and when an input to the second GPIO port changes from one binary input to another binary input.