IP Library Granted Patent US 8,236,603
Granted Patent B1
US 8,236,603 · App. 12/554,486 · Granted Aug 7, 2012

Polycrystalline semiconductor layers and methods for forming the same

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Quick Facts
Patent No.
US 8,236,603
App. No.
12/554,486
Granted
Aug 7, 2012
Kind
B1
Abstract

A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.

Claims (30)

1. A method for forming a semiconductor structure, the method comprising:

providing a polycrystalline substrate comprising a metal and having substantially randomly oriented grains;

forming, over the polycrystalline substrate, a buffer layer comprising a plurality of spaced-apart islands;

forming a semiconductor layer over the buffer layer;

forming a mask over the semiconductor layer; and

inducing relative motion, in a travel direction, between the polycrystalline substrate and a high-temperature region,

wherein one grain of the semiconductor layer grows from the mask preferentially in the travel direction, thereby forming a single-crystalline portion of the semiconductor layer.

2. The method of claim 1 , wherein, prior to the formation of the single-crystalline portion, the semiconductor layer has an average grain size approximately equal to an average spacing between the plurality of spaced-apart islands.

3. The method of claim 1 , wherein forming the semiconductor layer comprises depositing an initial semiconductor layer at a deposition temperature and annealing the initial semiconductor layer at an annealing temperature greater than the deposition temperature, thereby forming the semiconductor layer.

4. The method of claim 3 , wherein the annealing temperature is less than a melting point of the initial semiconductor layer.

5. The method of claim 1 , further comprising forming a photovoltaic device over the single-crystalline portion of the semiconductor layer.

6. The method of claim 5 , wherein the photovoltaic device comprises at least one of a p-n junction or a p-i-n junction.

7. The method of claim 1 , wherein forming the semiconductor layer comprises:

depositing an initial semiconductor layer in an amorphous state such that it retains residual stress after deposition; and

crystallizing the initial semiconductor layer into a polycrystalline state, thereby forming the semiconductor layer,

wherein the residual stress in the initial semiconductor layer provides at least a portion of a driving force for crystallizing the initial semiconductor layer.

8. The method of claim 1 , further comprising forming a capping layer over the semiconductor layer, the capping layer comprising at least one of Al, W, alumina, silicon dioxide, or silicon nitride.

9. The method of claim 1 , wherein forming the semiconductor layer comprises nucleating a grain at a location of each of the plurality of spaced-apart islands of the buffer layer.

10. The method of claim 1 , wherein the polycrystalline substrate comprises at least one of steel or a refractory metal.

11. The method of claim 1 , wherein the buffer layer comprises at least one of a metal, a metal alloy, or a dielectric material.

12. The method of claim 1 , wherein the buffer layer comprises at least one of Cu, Al, W, or Re.

13. The method of claim 1 , wherein the semiconductor layer comprises Ge.

14. The method of claim 1 , wherein the single-crystalline portion is greater than 50% of the semiconductor layer.

15. The method of claim 14 , wherein the single-crystalline portion is greater than 90% of the semiconductor layer.

16. The method of claim 1 , wherein forming the semiconductor layer comprises:

depositing an initial semiconductor layer;

forming a capping layer over the initial semiconductor layer; and

crystallizing the initial semiconductor layer, thereby forming the semiconductor layer.

17. The method of claim 16 , further comprising removing the capping layer from the semiconductor layer.

18. The method of claim 16 , wherein the capping layer comprises at least one of Al, W, alumina, silicon dioxide, or silicon nitride.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2020
From: SIVA POWER INC.
To: FIRST SOLAR, INC.
Reel/Frame 052197/0293 →
CHANGE OF NAME Recorded Mar 18, 2014
From: SOLEXANT CORP.
To: SIVA POWER, INC.
Reel/Frame 032463/0703 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2012
From: REALTIME DX, INC.
To: SOLEXANT CORP.
Reel/Frame 028172/0831 →
MERGER Recorded Jan 13, 2011
From: WAKONDA TECHNOLOGIES, INC.
To: REALTIME DX, INC.
Reel/Frame 025635/0211 →
SECURITY AGREEMENT Recorded Feb 10, 2010
From: WAKONDA TECHNOLOGIES, INC.
To: SILICON VALLEY BANK
Reel/Frame 023922/0513 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RERECORDING TO ADD ASSIGNEE PREVIOUSLY RECORDED ON REEL 023642 FRAME 0642. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 5, 2010
From: FRITZEMEIER, LESLIE G.; RAFFAELLE, RYNE P.; LEITZ, CHRISTOPHER
To: WAKONDA TECHNOLOGIES, INC.; ROCHESTER INSTITUTE OF TECHNOLOGY
Reel/Frame 023734/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2009
From: FRITZEMEIER, LESLIE G.; RAFFAELLE, RYNE P.; LEITZ, CHRISTOPHER
To: WAKONDA TECHNOLOGIES, INC.
Reel/Frame 023642/0642 →