Semiconductor memory device comprising a plurality of static memory cells
View Patent ↗A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
1. A semiconductor device comprising:
a plurality of static memory cells arranged in rows and columns;
a plurality of word lines arranged corresponding to the respective memory cell rows, each connected to the memory cells in the corresponding row,
a plurality of word line drivers arranged corresponding to said word lines, respectively, each driving the corresponding word line to a selected state,
a driver power supply line connected commonly to the plurality of word lines to supply a power supply voltage for the plurality of word lines,
a resistance element connected between a main power supply node and the driver power supply line,
a pull-down transistor connected between the driver power supply line and a ground node and
a control circuit connected to a gate electrode of the pull-down transistor and making the pull-down transistor be selectively on and off.
2. The semiconductor device according to claim 1 , wherein
the control circuit makes the pull-down transistor be on in accordance with a signal designating the plurality of word lines as one group.
3. The semiconductor device according to claim 1 , wherein
the pull-down transistor includes a plurality of unit transistors connected in parallel between the driver power supply line and the ground node.
4. The semiconductor device according to claim 1 , wherein
the resistance element is a passive resistance element different from a transistor element.
5. The semiconductor device according to claim 4 , wherein the passive resistance element is a polycrystalline silicon resistor.
6. The semiconductor device according to claim 5 , wherein
each memory cell includes an insulated gate field-effect transistor, and
the polycrystalline silicon resistor has an interconnection width substantially equal to a gate length defining a channel length of the insulated gate field-effect transistor.
7. The semiconductor device according to claim 1 , wherein
the resistance element is arranged in a region between a region for arranging the plurality of memory cells and a region for arranging the plurality of word drivers.
8. The semiconductor device according to claim 1 , wherein
the pull-down transistor is arranged in a region between a region for arranging the plurality of memory cells and a region for arranging the plurality of word drivers.