CMOS integrated circuit
View Patent ↗A CMOS IC according to the invention includes a discharging circuit for preventing electrostatic breakdown from occurring. The discharging circuit includes a discharging NMOSFET Qe, which couples a gate terminal node Vgp continuous to the gate of an outputting PDMOS transistor Q o and the gate of a discharging NMOSFET Qe via a capacitor Ce, and connects the drain of the discharging NMOSFET Qe to a gate terminal node Vgp continuous to the gate terminal of the outputting PDMOS transistor Q o . The discharging circuit 300 also includes a pull-down resistor disposed between the gate of the discharging NMOSFET Qe and the ground for preventing the discharging NMOSFET Qe from operating in a steady state condition. The CMOS IC according to the invention makes the discharging NMOSFET Qe trigger to operate by the potential change at the node corresponding to the potential change of the power supply line, when a surge caused by static electricity and such is applied to the power supply line.
1. An apparatus comprising:
a power supply line;
a discharging switch, wherein the discharging switch is triggered to operate by a potential change of the power supply line or by a potential change at a node corresponding to the potential change of the power supply line, the discharging switch comprising an N-channel MOSFET comprising a gate terminal and a drain terminal, wherein the gate terminal of the N-channel MOSFET is coupled with the power supply line or with the node, the potential change thereat corresponds to the potential change of the power supply line, via a capacitor, and wherein the drain terminal of the N-channel MOSFET is connected to the node, the potential change thereat corresponds to the potential change of the power supply line; and
a CMOS integrated circuit that makes the discharging switch operate when a surge is applied to the power supply line in order to protect devices in the CMOS integrated circuit from a voltage caused by the surge, said CMOS integrated circuit comprising an operational amplifier comprising an output terminal, and an outputting transistor comprising a gate terminal connected to the output terminal of the operational amplifier; wherein the operational amplifier further comprises a differential amplifying stage, an output stage, and a feedback circuit comprising a feedback resistor and a feedback capacitor connected in series to each other; wherein the feedback circuit is connected between an output terminal of the output stage working for the output terminal of the operational amplifier and an output terminal of the differential amplifying stage; and wherein the drain terminal of the N-channel MOSFET constituting the discharging switch is connected to the output terminal of the operational amplifier.
2. The apparatus according to claim 1 , wherein the CMOS integrated circuit further comprises a pull-down resistor between the gate terminal of the N-channel MOSFET and a ground.
3. The apparatus according to claim 1 , wherein the CMOS integrated circuit comprises a series regulator circuit.