IP Library Granted Patent US 8,232,142
Granted Patent B2
US 8,232,142 · App. 12/558,824 · Granted Jul 31, 2012

Self-aligned silicon carrier for optical device supporting wafer scale methods

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Quick Facts
Patent No.
US 8,232,142
App. No.
12/558,824
Granted
Jul 31, 2012
Kind
B2
Abstract

Disclosed is a carrier assembly for and a method of manufacturing an optical device. The method comprises providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly; providing a corresponding number of through holes in the silicon substrate to permit the passage of light therethrough and further providing guide holes in the silicon substrate to present means for passive alignment of an external optical connection; and dicing the optical device carrier assembly to form individual optical devices. Preferably, the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux, the through holes are dry etched into the silicon substrate, and/or the volume between the optical die and silicon substrate is filled with a transparent polymer. Preferably, the transparent polymer is silicone rubber or epoxy. Preferably, the optical dies have a polymer mass to assist the heat transfer to the silicon substrate.

Claims (7)

1. A method for manufacturing an optical device, the method comprising:

providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly, wherein the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux; dry etching a corresponding number of through holes into the silicon substrate to permit the passage of light therethrough; dicing the optical device carrier assembly to form individual optical devices; and using the through holes as guide holes to permit passive fiber alignment of the optical carrier to an external optical element in use, wherein guide pins are used to align the through holes in the silicon substrate with corresponding guide holes in the external optical element; whereby the through holes serve to provide both optical transparency in the silicon substrate and serve to provide a micromechanical structure for passive fiber alignment.

2. The method of claim 1 , further comprising the step of filling the volume between the optical die and silicon substrate with a transparent polymer.

3. The method of claim 2 , wherein the transparent polymer is silicone rubber or epoxy.

4. The method of claim 1 , further comprising testing and burn in of the optical dies prior to the dicing step.

5. The method of claim 1 , further comprising providing the optical dies with a polymer mass to assist the heat transfer to the silicon substrate.

6. The method of claim 1 , further comprising providing a metal pattern on the silicon substrate and solder bumps on an epi side of each optical die, and wherein the step of mounting the optical dies to the substrate includes mating together the metal pattern and the solder bumps.

Assignments (3)
CORRECTIVE ASSIGNMENT TO REMOVE SECOND ASSIGNEE PREVIOUSLY RECORDED ON REEL 026272, FRAME 0772 Recorded Jul 7, 2011
From: ZARLINK SEMICONDUCTOR INC.; ZARLINK SEMICONDUCTOR AB
To: TYCO ELECTRONICS SERVICES GMBH
Reel/Frame 026619/0271 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2011
From: ZARLINK SEMICONDUCTOR INC; ZARLINK SEMICONDUCTOR AB
To: TYCO ELECTRONICS SERVICES GMBH; GOLDCUP 5514 AB UNAT TYCO ELECTRONICS SVENSKA HOLDINGS AB
Reel/Frame 026272/0772 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2009
From: STEIJER, ODD ROBERT; ANDERSSON, HANS MAGNUS EMIL
To: ZARLINK SEMICONDUCTOR AB
Reel/Frame 023692/0567 →