Memory controller interface
View Patent ↗A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous dynamic random access memory SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.
1. A method, comprising:
receiving at a memory controller interface an access request for data stored in a NAND flash component in communication with the memory controller interface, said access request being received from a processor designed to support NOR flash and static random access memory (SRAM) components;
identifying at the memory controller interface a sector of the NAND flash component comprising the requested data;
checking at least one tag entry at the memory controller interface to determine if the data of the identified sector had been previously stored in a cache provided by a synchronous dynamic random access memory (SDRAM) component in communication with said memory controller interface;
if the data of the identified sector had not been previously stored in the cache, then:
reading the requested data from the NAND flash component;
writing the requested data to the cache; and
responding to the access request by reading the data corresponding to the identified sector from the cache.
2. The method of claim 1 , further comprising, if the data of the identified sector had not been previously stored in the cache:
determining whether space is available in the cache to write the requested data to the cache;
if cache space is available, writing the requested data in an available sector of the cache;
if cache space is not available, checking at least one tag entry at the memory controller interface to determine if data in a sector of the cache is unmodified; and
if a cache sector of unmodified data is identified, overwriting the cache sector with the requested data.
3. The method of claim 2 , further comprising, if cache space is not available and no cache sector of unmodified data is identified:
reading out one or more sectors of modified data from the cache and writing said modified data to the corresponding sectors of the NAND flash component; and
overwriting at least one of said cache sectors with the requested data.
4. The method of claim 1 , further comprising:
in response to a request from said processor, modifying data stored in an identified sector of the cache; and
writing the modified data to the NAND flash component.
5. The method of claim 4 , further comprising:
when data stored in an identified sector of the cache is modified, setting at the memory controller interface a tag entry corresponding to the identified cache sector to indicate that the data has been modified;
when the modified data is written to the NAND flash, setting said tag entry corresponding to the identified cache sector to indicate that the data has not been modified.
6. The method of claim 5 , wherein writing the modified data to the NAND flash component occurs when:
all cache sectors contain modified data;
a loss of power is detected;
an autosave procedure is initiated; or
the processor requests that modified data be written from the cache to the NAND flash component.
7. The method of claim 1 , further comprising performing error correction coding on the requested data read from the NAND flash component.
8. The method of claim 1 wherein receiving the access request comprises receiving a request for boot code stored in the NAND flash, the method further comprising:
scanning the requested boot code for a predetermined signature;
if the predetermined signature is found, designating at least a portion of the NAND flash to be read only.
9. The method of claim 8 wherein receiving the access request is preceded by a power on reset.
10. A data processing device comprising a memory controller interface configured to carry out the method of claim 1 .
11. A data processing device comprising a memory controller interface configured to carry out the method of claim 2 .
12. A data processing device comprising a memory controller interface configured to carry out the method of claim 3 .
13. A data processing device comprising a memory controller interface configured to carry out the method of claim 4 .
14. A data processing device comprising a memory controller interface configured to carry out the method of claim 5 .
15. A data processing device comprising a memory controller interface configured to carry out the method of claim 6 .
16. A data processing device comprising a memory controller interface configured to carry out the method of claim 8 .
17. A data processing device comprising a memory controller interface configured to carry out the method of claim 9 .