Vertical alignment display device with enhanced contrast
A vertical alignment liquid crystal display includes two sub-pixels each with a variable capacitor. A pixel is bisected into a high gray sub-pixel and a low gray sub-pixel through forming a variable capacitor at each sub-pixel. With this structure, the sub-pixels express different grays so that lateral visibility is enhanced. It is not required in bisecting a pixel into two sub-pixels to form separate wires for applying different signals thereto, and the amount of data to be processed at the driver for driving the display device is reduced. Furthermore, a pixel is bisected into two sub-pixels with variable capacitors in a simplified manner, and it is not required to form additional wires and elements, so the aperture ratio is enhanced.
1. A display device comprising:
a plurality of gate lines;
a plurality of data lines; and
a pixel connected to one of the plurality of gate lines and one of the plurality of data lines, the pixel comprising first and second sub-pixels,
wherein the first sub-pixel comprises:
a first thin film transistor having control and input terminals connected to at least one of the gate and data lines, respectively; and
a first liquid crystal capacitor and a first variable capacitor respectively connected to an output terminal of the first thin film transistor, and
wherein the second sub-pixel comprises:
a second thin film transistor having control and input terminals connected to at least one of the gate and data lines, respectively; and
a second liquid crystal capacitor and a second variable capacitor respectively connected to an output terminal of the second thin film transistor,
wherein the first and second variable capacitors are formed each with a thin film transistor comprising a gate electrode, a semiconductor layer, a source electrode, and a drain electrode, wherein the source and drain electrodes are electrically connected to each other, and
wherein the source and drain electrodes of the first variable capacitor are respectively connected to the output terminal of the first thin film transistor, and the gate electrode of the second variable capacitor is connected to the output terminal of the second thin film transistor.
2. The display device of claim 1 , wherein the first and second variable capacitors have a first capacitance upon receiving a voltage equal to or exceeding a predetermined voltage, and wherein the first capacitance is stored at a region where the semiconductor layer and the source and drain electrodes overlap with the gate electrode.
3. The display device of claim 1 , wherein the first and second variable capacitors have a second capacitance upon receiving a voltage that is less than a predetermined voltage, and wherein the second capacitance is stored at a region where the source and drain electrodes overlap with the gate electrode.
4. The display device of claim 1 , further comprising an ohmic contact layer formed between the source and drain electrodes and the semiconductor layer.
5. The display device of claim 4 , wherein the second capacitance is stored at a region where the ohmic contact layer and the source and drain electrodes overlap with the gate electrode.
6. A display device comprising:
a plurality of gate lines;
a plurality of data lines; and
a pixel connected to one of the plurality of gate lines and one of the plurality of data lines,
wherein the pixel comprises a thin film transistor with control and input terminals connected to at least one of the gate and data lines, respectively, and a liquid crystal capacitor and a variable capacitor respectively connected to an output terminal of the thin film transistor, wherein the variable capacitor is formed with the thin film transistor;
wherein the first and second variable capacitors are formed each with a thin film transistor comprising a gate electrode, a semiconductor layer, a source electrode, and a drain electrode, wherein the source and drain electrodes are electrically connected to each other, and
wherein the source and drain electrodes of the first variable capacitor are respectively connected to the output terminal of the first thin film transistor, and the gate electrode of the second variable capacitor is connected to the output terminal of the second thin film transistor.