IP Library Granted Patent US 8,392,787
Granted Patent B2
US 8,392,787 · App. 12/561,374 · Granted Mar 5, 2013

Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding

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Quick Facts
Patent No.
US 8,392,787
App. No.
12/561,374
Granted
Mar 5, 2013
Kind
B2
Abstract

Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows.

Claims (62)

1. An apparatus, comprising:

an LDPC (Low Density Parity Check) matrix processing circuitry that is operative to modify a first LDPC matrix thereby generating a second LDPC matrix by performing at least one of:

selective merging at least two sub-matrix rows of the first LDPC matrix into a singular sub-matrix row of the second LDPC matrix;

selective deleting a sub-matrix row of the first LDPC matrix; and

partial re-using of only selected sub-matrix rows, being fewer than all sub-matrix rows, of the first LDPC matrix; and

a decoder circuitry, coupled to the LDPC matrix processing circuitry, that is operative to employ the second LDPC matrix to decode an LDPC coded signal thereby generating an estimate of an information bit encoded therein.

2. The apparatus of claim 1 , wherein:

the LDPC matrix processing circuitry is operative to modify the first LDPC matrix thereby generating the second LDPC matrix by performing partitioning of a plurality of sub-matrix rows of the first LDPC matrix into a plurality of layers of the second LDPC matrix; and

the decoder circuitry comprises a Belief Propagation (BP) decoder circuitry that is operative to perform layered BP decoding on the plurality of layers of the second LDPC matrix.

3. The apparatus of claim 2 , wherein:

at least one of the plurality of layers of the second LDPC matrix includes at least two sub-matrix rows of the second LDPC matrix.

4. The apparatus of claim 2 , wherein:

a first of the plurality of layers of the second LDPC matrix includes at least two sub-matrix rows of the second LDPC matrix; and

a second of the plurality of layers of the second LDPC matrix includes a singular sub-matrix row of the second LDPC matrix.

5. The apparatus of claim 1 , further comprising:

an LDPC generator matrix generation circuitry, coupled to the LDPC matrix processing circuitry, that is operative to process the first LDPC matrix or the second LDPC matrix thereby generating an LDPC generator matrix; and

an encoder circuitry that is operative to employ the LDPC generator matrix to encode at least one additional information bit thereby generating at least one additional LDPC coded signal.

6. The apparatus of claim 1 , wherein:

the LDPC matrix processing circuitry is operative to replace an all-zero valued sub-matrix within a sub-matrix row of the first LDPC matrix with a CSI sub-matrix in accordance with generating the second LDPC matrix.

7. The apparatus of claim 1 , wherein:

the LDPC matrix processing circuitry is operative to replace a CSI sub-matrix within a sub-matrix row of the first LDPC matrix with an all-zero valued sub-matrix in accordance with generating the second LDPC matrix.

8. The apparatus of claim 1 , wherein:

the apparatus is a wireless communication device.

9. The apparatus of claim 1 , wherein:

the apparatus is a communication device;

the communication device is a transceiver or a receiver.

10. The apparatus of claim 1 , wherein:

the apparatus is a communication device; and

the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

11. An apparatus, comprising:

an LDPC (Low Density Parity Check) matrix processing circuitry that is operative to modify a first LDPC matrix thereby generating a second LDPC matrix, that is partitioned into a plurality of layers, by performing at least one of:

selective merging at least two sub-matrix rows of the first LDPC matrix into a singular sub-matrix row of the second LDPC matrix;

selective deleting a sub-matrix row of the first LDPC matrix; and

partial re-using of only selected sub-matrix rows, being fewer than all sub-matrix rows, of the first LDPC matrix; and

a decoder circuitry, coupled to the LDPC matrix processing circuitry, that is operative to employ the second LDPC matrix to decode an LDPC coded signal, in accordance with Belief Propagation (BP) decoding processing to perform layered BP decoding on the plurality of layers of the second LDPC matrix, thereby generating an estimate of an information bit encoded therein; and wherein:

at least one of the plurality of layers of the second LDPC matrix includes at least two sub-matrix rows of the second LDPC matrix.

12. The apparatus of claim 11 , wherein:

at least one additional of the plurality of layers of the second LDPC matrix includes a singular sub-matrix row of the second LDPC matrix.

13. The apparatus of claim 11 , further comprising:

an LDPC generator matrix generation circuitry, coupled to the LDPC matrix processing circuitry, that is operative to process the first LDPC matrix or the second LDPC matrix thereby generating an LDPC generator matrix; and

an encoder circuitry that is operative to employ the LDPC generator matrix to encode at least one additional information bit thereby generating at least one additional LDPC coded signal.

14. The apparatus of claim 11 , wherein:

the LDPC matrix processing circuitry is operative to replace an all-zero valued sub-matrix within a sub-matrix row of the first LDPC matrix with a CSI sub-matrix in accordance with generating the second LDPC matrix.

15. The apparatus of claim 11 , wherein:

the LDPC matrix processing circuitry is operative to replace a CSI sub-matrix within a sub-matrix row of the first LDPC matrix with an all-zero valued sub-matrix in accordance with generating the second LDPC matrix.

16. The apparatus of claim 11 , wherein:

the apparatus is a communication device; and

the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

17. A method, comprising:

modifying a first LDPC matrix thereby generating a second LDPC matrix by performing at least one of:

selectively merging at least two sub-matrix rows of the first LDPC matrix into a singular sub-matrix row of the second LDPC matrix;

selectively deleting a sub-matrix row of the first LDPC matrix; and

partially re-using of only selected sub-matrix rows, being fewer than all sub-matrix rows, of the first LDPC matrix; and

operating a decoder circuitry that uses the second LDPC matrix to decode an LDPC coded signal thereby generating an estimate of an information bit encoded therein.

18. The method of claim 17 , further comprising:

processing the first LDPC matrix or the second LDPC matrix thereby generating an LDPC generator matrix; and

operating an encoder circuitry that uses the LDPC generator matrix to encode at least one additional information bit thereby generating at least one additional LDPC coded signal.

19. The method of claim 17 , further comprising:

replacing an all-zero valued sub-matrix within a sub-matrix row of the first LDPC matrix with a CSI sub-matrix in accordance with generating the second LDPC matrix.

20. The method of claim 17 , wherein:

the method is performed in a communication device; and

the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2009
From: SHEN, BA-ZHONG; BLANKSBY, ANDREW J.; TRACHEWSKY, JASON A.
To: BROADCOM CORPORATION
Reel/Frame 023244/0365 →