Media access control security management in physical layer

1. A system comprising:

a media access control (MAC) security (MACsec) function block configured to implement MACsec protocols on a network;

a physical layer device (PHY) connected to the MACsec function block, the PHY including an interface register configured to store command information for the MACsec function block;

a central processing unit (CPU) configured to provide the command information for the MACsec function block to the PHY via a management data input/output (MDIO) bus;

wherein the PHY is configured to:

execute either a read command or a write command against the MACsec function block based on the command information,

receive, from the MACsec function block, a response corresponding to the execution of the read command or write command against the MACsec function block; and

provide the response to the CPU via the MDIO bus;

wherein the interface register includes at least a command register, an address register and a data register configured to store the command information, wherein the data register comprises two 16 bit registers in the interface register, and wherein the CPU is configured to perform multiple reads or writes for data, associated with the command, that occupies more than 32 bits.

2. The system of claim 1 , wherein the MACsec function block comprises a plurality of gigabit media independent interfaces (GMIIs).

3. The system of claim 1 , wherein the MACsec function block provides resources for the PHY that correspond to an institute of electrical and electronics engineers (IEEE) 802.1 AE standard for implementing the MACsec protocols on the network.

4. The system of claim 1 , wherein the MACsec function block enables the network to provide secure and encrypted communication on the network based on the MACsec protocols.

5. The system of claim 1 , wherein the PHY includes two MDIO ports, each MDIO port corresponding to an interface register, wherein the CPU and PHY communicate via the two MDIO ports operating in parallel.

6. The system of claim 5 , wherein the PHY comprises an arbitration unit configured to arbitrate access to the MACsec function block between the two interface registers and select one of the interface registers to which to provide access to the MACsec function block.

7. The system of claim 1 , wherein the MDIO bus is configured to transmit 5 bits of address space between the CPU and the PHY, wherein the 5 bits of address space correspond to a portion of an interface register of the PHY.

8. The system of claim 7 , wherein the CPU is configured to provide a MACsec address using the 5 bits of address space, wherein the PHY is configured to store the MACsec address and map the MACsec address to a corresponding to a portion of the MACsec function block.

9. The system of claim 1 , wherein the CPU is configured to operate as an MDIO master and provide the command to the PHY that is configured to operate as an MDIO slave and execute the read or write command against the MACsec function block.

10. A method comprising:

receiving, at a first media data input/output (MDIO) port of a physical layer device (PHY) of a network, command information, from a central processing unit (CPU) to access a media access control (MAC) security (MACsec) function block, wherein a plurality of MDIO ports connect the PHY and CPU;

determining from the command information:

whether the command information includes a read command or a write command,

if the command is the write command, write data to be written to the MACsec function block, and

the length of the data to be read or written, and

an address corresponding to a portion of the MACsec function block of which to read data from or write the data to based on the command information;

executing the read command or write command against the MACsec function block based on the determined command information;

receiving, at the PHY, a result of the execution, the result including an acknowledgement of the write command or the data read from the MACsec function block based on the read command; and

providing the result of the execution to the CPU via the first MDIO port of the PHY;

wherein the determining includes:

determining whether the command is a burst read command, wherein the burst read command indicates several portions of the MACsec function block which to read;

determining an initial address of the MACsec function block at which to start the burst read command; and

determining a data length corresponding to the burst read command.

11. The method of claim 10 , wherein the receiving the command information comprises:

receiving first command information from the CPU at the first MDIO port of the PHY, the first MDIO port being associated with a first interface register configured to store the first command information;

receiving second command information from the CPU at a second MDIO port of the PHY, wherein the second MDIO port operates in parallel with the first MDIO port, the second MDIO port being associated with a second interface register configured to store the second command information; and

arbitrating access to the MACsec function block between the first interface register and the second interface register.

12. The method of claim 10 , wherein the executing comprises:

determining that a timer expires prior to a completion of the execution of the read command or write command;

interrupting the read command or write command;

notifying the CPU that the execution failed; and

executing a subsequent command.

13. The method of claim 10 , wherein the executing comprises:

accessing a memory space of the MACsec function block corresponding to the address of a write command;

retrieving data from the memory space into a register space of the MACsec function block;

manipulating the data in the register space; and

writing the manipulated data to the memory space.

14. The method of claim 10 , wherein the executing comprises:

accessing a memory space of the MACsec function block corresponding to the address of a read command;

storing data from the memory space into a register space of the MACsec function block; and

providing the data from the register space to the PHY as the result.

15. The method of claim 11 further comprising:

determining that a first interface register associated with a first MDIO port configured to store the command information is non-functional;

determining that a second interface register associated with a second MDIO port configured to store the command information is functional; and

resetting the first interface register, without impacting the second interface register.

16. A system comprising:

a media access control (MAC) security (MACsec) function block configured to implement MACsec protocols on a network;

a physical layer device (PHY) connected to the MACsec function block, the PHY including an interface register configured to store command information for the MACsec function block;

a central processing unit (CPU) configured to provide the command information for the MACsec function block to the PHY via a management data input/output (MDIO) bus;

wherein the PHY is configured to execute either a read command or a write command against the MACsec function block based on the command information,

wherein the interface register includes at least a command register, an address register and a data register configured to store the command information, wherein the data register comprises two 16 bit registers in the interface register, and wherein the CPU is configured to perform multiple reads or writes for data, associated with the command, that occupies more than 32 bits.

17. The system of claim 16 , wherein the MACsec function block enables the network to provide secure and encrypted communication on the network based on the MACsec protocols.

18. The system of claim 16 , wherein the PHY includes two MDIO ports, each MDIO port corresponding to an interface register, wherein the CPU and PHY communicate via the two MDIO ports operating in parallel.

19. The system of claim 18 , wherein the PHY comprises an arbitration unit configured to arbitrate access to the MACsec function block between the two interface registers and select one of the interface registers to which to provide access to the MACsec function block.

20. The system of claim 16 , wherein the MDIO bus is configured to transmit 5 bits of address space between the CPU and the PHY, wherein the 5 bits of address space correspond to a portion of an interface register of the PHY.

21. The system of claim 20 , wherein the CPU is configured to provide a MACsec address using the 5 bits of address space, wherein the PHY is configured to store the MACsec address and map the MACsec address to a corresponding to a portion of the MACsec function block.

22. The system of claim 16 , wherein the CPU is configured to operate as an MDIO master and provide the command to the PHY that is configured to operate as an MDIO slave and execute the read or write command against the MACsec function block.

23. A method comprising:

receiving, at a first media data input/output (MDIO) port of a physical layer device (PHY) of a network, command information, from a central processing unit (CPU) to access a media access control (MAC) security (MACsec) function block, wherein a plurality of MDIO ports connect the PHY and CPU;

determining from the command information:

whether the command information includes a read command or a write command,

if the command is the write command, write data to be written to multiple portions of the MACsec function block, and

the length of the data to be read or written, and

an address corresponding to a portion of the MACsec function block of which to read data from or write the data to based on the command information;

executing the read command or write command against the MACsec function block based on the determined command information;

receiving, at the PHY, a result of the execution, the result including an acknowledgement of the write command or the data read from the MACsec function block based on the read command; and

providing the result of the execution to the CPU via the first MDIO port of the PHY;

wherein the determining includes:

wherein the determining comprises:

determining whether the command is a burst write command, wherein the burst write command indicates several portions of the MACsec function block which to write;

determining an initial address of the MACsec function block at which to start the burst write command;

determining a data length corresponding to the burst write command; and

determining the write data to be written.