IP Library Granted Patent US 8,560,875
Granted Patent B2
US 8,560,875 · App. 12/561,919 · Granted Oct 15, 2013

Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode

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Quick Facts
Patent No.
US 8,560,875
App. No.
12/561,919
Granted
Oct 15, 2013
Kind
B2
Abstract

An apparatus for clock calibration on a remote device includes a first oscillator, a second oscillator, and a clock calibration module. The first oscillator generates a first clock signal during an active communication mode to facilitate communications between the remote and host devices. The first oscillator is inactive during a sniff mode. The second oscillator generates a second clock signal during both the active communication and sniff modes. The clock calibration module generates an estimated count for the first clock signal approximately at a transition from the sniff mode to the active communication mode. The estimated count is based on a clock ratio of a baseline count of the first clock signal relative to a baseline count of the second clock signal. The clock calibration module also calculates a difference between the estimated count and an actual count from the host device to determine whether to update the clock ratio.

Claims (168)

1. An apparatus for clock calibration on a remote device, the apparatus comprising:

a first oscillator to generate a first clock signal during an active communication mode of the remote device to facilitate communications between the remote device and a host device, wherein the first oscillator is inactive during a sniff mode of the remote device;

a second oscillator to generate a second clock signal during both the active communication and sniff modes, wherein the second oscillator consumes less power than the first oscillator; and

a clock calibration module coupled to the first and second oscillators, the clock calibration module to:

generate an estimated count for the first clock signal approximately at a transition from the sniff mode to the active communication mode, wherein the estimated count for the first clock signal is based on a clock ratio of a baseline count of the first clock signal relative to a baseline count of the second clock signal;

calculate a difference between the estimated count for the first clock signal and an actual count from the host device to determine whether to update the clock ratio;

forego updating the clock ratio in response to a determination that an incremental count of the second clock signal approximately during the sniff mode is less than a threshold amount; and

update the clock ratio , according to the following algorithm:

Δ

(

t

01

-

t

00

)

=

Δ

T

(

t

11

-

t

10

)

(

t

12

-

t

11

)

,

in which Δ(t 01 −t 00 ) represents an adjustment amount applied to the baseline count of the first clock signal, ΔT represents a calibration factor which is the difference between the estimated count for the first clock signal and the actual count from the host device, (t 11 −t 10 ) represents the baseline count of the second clock signal, and (t 12 −t 11 ) represents the incremental count of the second clock signal approximately during the sniff mode.

2. The apparatus of claim 1 , wherein the second clock signal from the second oscillator has a lower frequency and is less accurate than the first clock signal from the first oscillator.

3. The apparatus of claim 1 , wherein the clock calibration module is configured to update the clock ratio based on a determination that the estimated count for the first clock signal is different from the actual count from the host device.

4. The apparatus of claim 3 , wherein the clock calibration module is configured to update the clock ratio by adjusting the baseline count of the first clock signal.

5. The apparatus of claim 3 , wherein the clock calibration module is configured to update the clock ratio further based on the baseline count of the second clock signal and an incremental count of the second clock signal.

6. The apparatus of claim 1 , wherein the clock calibration module is configured to update the clock ratio during the active communication mode while the first clock signal is active.

7. The apparatus of claim 1 , wherein the clock calibration module is further configured to synchronize the estimated count for the first clock signal with the actual count from the host device by setting the estimated count for the first clock signal to the actual count from the host device.

8. The apparatus of claim 7 , wherein the clock calibration module is configured to synchronize the estimated count for the first clock signal with the actual count from the host device during the active communication mode.

9. The apparatus of claim 1 , further comprising an electronic memory device coupled to the clock calibration module, the electronic memory device to store the baseline count for the first clock signal, the baseline count for the second clock signal, the estimated count for the first clock signal, and the actual count from the host device.

10. The apparatus of claim 9 , further comprising a processor coupled to the electronic memory device to facilitate calculating the difference between the estimated count for the first clock signal and the actual count from the host device, wherein the processor comprises:

an integer multiplier;

an integer divider; and

a bit shifter, wherein the bit shifter is configured to left-shift bits of a dividend prior to a division operation and to right-shift bits of a product after a multiplication operation.

11. A method for clock calibration on a remote device, the method comprising:

generating a first clock signal exclusively during an active communication mode of the remote device to facilitate communications between the remote device and a host device;

generating a second clock signal during both the active communication mode and a sniff mode;

generating an estimated count for the first clock signal approximately at a transition from the sniff mode to the active communication mode, wherein the estimated count for the first clock signal is based on a clock ratio of a baseline count of the first clock signal relative to a baseline count of the second clock signal;

calculating a difference between the estimated count for the first clock signal and an actual count from the host device to determine whether to update the clock ratio;

foregoing an update of the clock ratio in response to a determination that an incremental count of the second clock signal approximately during the sniff mode is less than a threshold amount; and

updating the clock ratio, wherein updating the clock ration further comprises adjusting the baseline count of the first clock signal relative to the baseline count of the second clock signal based on an incremental count of the second clock signal, according to the following algorithm:

Δ

(

t

01

-

t

00

)

=

Δ

T

(

t

11

-

t

10

)

(

t

12

-

t

11

)

,

in which Δ(t 01 −t 00 ) represents an adjustment amount applied to the baseline count of the first clock signal, ΔT represents a calibration factor which is the difference between the estimated count for the first clock signal and the actual count from the host device, (t 11 −t 10 ) represents the baseline count of the second clock signal, and (t 12 −t 11 ) represents the incremental count of the second clock signal approximately during the sniff mode.

12. The method of claim 11 , further comprising updating the clock ratio based on a determination that the estimated count for the first clock signal is different from the actual count from the host device.

13. The method of claim 11 , further comprising calculating the difference between the estimated count for the first clock signal and the actual count from the host device during the active communication mode.

14. The method of claim 11 , further comprising synchronizing the estimated count for the first clock signal with the actual count from the host device by setting the estimated count for the first clock signal to the actual count from the host device during the active communication mode.

15. A computer program product comprising:

a non-transitory electronic memory device to store instructions which, when executed on a computer processor, cause the computer processor to implement operations comprising:

compute a clock ratio a baseline count of the first clock signal relative to a baseline count of the second clock signal, wherein the first clock signal is exclusively operational during an active communication mode, and the second clock signal is operational during both the active communication mode and a sniff mode;

generate an estimated count for the first clock signal approximately at a transition from the sniff mode to the active communication mode;

receive and store an actual count from a host device;

calculate a difference between the estimated count for the first clock signal and the actual count from the host device;

determine whether to update the clock ratio based on the difference between the estimated count for the first clock signal and the actual count from the host device;

forego the update of the clock ratio in response to a determination that an incremental count of the second clock signal approximately during the sniff mode is less than a threshold amount; and

update the clock ratio, based on a determination that the estimated count for the first clock signal is different from the actual count from the host device, according to the following algorithm:

Δ

(

t

01

-

t

00

)

=

Δ

T

(

t

11

-

t

10

)

(

t

12

-

t

11

)

,

in which Δ(t 01 −t 00 ) represents an adjustment amount applied to the baseline count of the first clock signal, ΔT represents a calibration factor which is the difference between the estimated count for the first clock signal and the actual count from the host device, (t 11 −t 10 ) represents the baseline count of the second clock signal, and (t 12 −t 11 ) represents the incremental count of the second clock signal approximately during the sniff mode.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
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MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2009
From: SHEN, KANG
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
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