IP Library Granted Patent US 8,212,287
Granted Patent B2
US 8,212,287 · App. 12/562,675 · Granted Jul 3, 2012

Nitride semiconductor structure and method of making same

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Quick Facts
Patent No.
US 8,212,287
App. No.
12/562,675
Granted
Jul 3, 2012
Kind
B2
Abstract

A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides sign0ificant blocking of both vertically and diagonally running defects during growth.

Claims (18)

1. A semiconductor structure, comprising:

a wurtzitic nitride substrate having a growth surface defining a growth plane, said growth plane corresponding to a crystallographic plane forming an angle α other than 0 or 90 degrees to the primary crystallographic plane of the substrate;

a nitride-based growth medium disposed over said substrate; and

structural sidewalls extending substantially normal to said growth plane and defining a plurality of window openings, said window openings having a width, w, and a height, h, said window openings further having formed therein a portion of said nitride-based growth medium such that crystallographic defects which originate at a portion of said growth surface and have an angular orientation substantially parallel to the orientation of said crystallographic plane of said substrate substantially terminate at said sidewalls and thereby substantially do not extend beyond the height of said window openings.

2. The semiconductor structure of claim 1 , further comprising a dielectric layer formed over said growth surface of said substrate, said dielectric layer patterned to form islands, and wherein said structural sidewalls are sidewalls of said islands.

3. The semiconductor structure of claim 1 , wherein said substrate is patterned to have trenches formed therein, and wherein said sidewalls are sidewalls of said trenches.

4. The semiconductor structure of claim 1 , wherein said substrate comprises semi-polar GaN(1122).

5. The semiconductor structure of claim 1 , further comprising nitride-based growth medium formed over and in physical contact with said nitride-based growth medium formed in a plurality of said window openings.

6. The semiconductor structure of claim 1 , further comprising post structures said post structures:

formed of said nitride-based growth medium;

formed over said nitride-based growth medium formed in said window openings to a height h over said growth surface;

formed to have sidewall facets; and

formed to be inclined at an angle, β, relative to said growth plane and out of normal to said growth plane;

whereby, crystallographic defects which originate at a portion of said growth surface and have an orientation substantially normal to said crystallographic plane substantially terminate at said facets and thereby substantially do not extend beyond the height h of said post structures.

7. The semiconductor structure of claim 6 , further comprising nitride-based growth medium formed over and in physical contact with a plurality of said post structures.

8. The semiconductor structure of claim 1 , further comprising a dielectric layer formed over and in contact with said growth surface, and further wherein said height, h, is the distance between an upper surface of said dielectric layer and said growth surface, and is at least equal to the product of the width, w, and the cotangent of the angle α.

9. The semiconductor structure of claim 8 , wherein said dielectric layer comprises silicon nitride (SiN x ), said nitride-based growth medium comprises gallium nitride (GaN), and said substrate comprises semi-polar GaN(1122).

10. The semiconductor structure of claim 8 , wherein said dielectric layer comprises silicon nitride (SiN x ), said nitride-based growth medium comprises gallium nitride (GaN), and said substrate comprises semi-polar GaN(1122).

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073842/0479 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →