Quantum well graphene structure
View Patent ↗An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the charged defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons.
1. An electronic device, comprising:
an under-layer constructed of a highly ordered crystalline material having a high dielectric constant;
an over-layer constructed of a crystalline material having a high dielectric constant; and
a layer of n-graphene located between the over-layer and the under-layer;
wherein the under-layer has a substantially atomically flat surface that contacts the n-graphene layer, with root mean square roughness of less than 0.5 nm.
2. The electronic device as in claim 1 wherein the n-graphene layer consists of a single layer of graphene.
3. The electronic device as in claim 1 wherein the n-graphene layer comprises a plurality of layers of graphene.
4. The electronic device as in claim 1 wherein the n-graphene layer consists of 1 to 10 layers of graphene.
5. The electronic device as in claim 1 wherein the n-graphene layer is sandwiched between and contacts each of the under-layer and over-layer.
6. The electronic device as in claim 1 wherein the over-layer has a substantially atomically flat surface that contacts the n-graphene layer, with root mean square roughness of less than 0.5 nm.
7. The electronic device as in claim 1 wherein the under-layer and/or over-layer have a dielectric constant of at least 4.
8. The electronic device as in claim 1 further comprising a plurality of electrically conductive leads connected with the n-graphene layer for supplying charge carriers to the graphene layer.
9. The electronic device as in claim 1 wherein the device is a field effect transistor.
10. The electronic device as in claim 1 wherein the device is a magnetoresistive sensor.
11. An electronic device, comprising:
an under-layer constructed of a highly ordered crystalline material having a high dielectric constant;
an over-layer constructed of a crystalline material having a high dielectric constant; and
a layer of n-graphene located between the over-layer and the under-layer;
wherein the under-layer and over-layer have a substantially atomically flat surface that contacts the n-graphene layer, with root mean square roughness of less than 0.5 nm.
12. An electronic device, comprising:
an n-graphene layer;
first and second interfacial layers comprising a non-polar dielectric material, the n-graphene layer being sandwiched between the first and second interfacial layers;
an under-layer comprising a crystalline material having a high dielectric constant; and
an over-layer comprising a crystalline material having a high dielectric constant; wherein
the n-graphene layer and first and second interfacial layers are sandwiched between the under-layer and the over-layer;
wherein the under-layer has a substantially atomically flat surface that contacts the n-graphene layer, with root mean square roughness of less than 0.5 nm.
13. The electronic device as in claim 12 wherein the each of the interfacial layers comprises a material having a weak frequency dependence of its dielectric constant.
14. The electronic device as in claim 12 wherein each of the interfacial layers is no greater than 10 nm thick.
15. The electronic device as in claim 12 wherein the first and second interfacial layers each comprise self-assembled monolayers such as: 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a-methylstyrene) or nanometer-thick layers of polymers such as polyethylene, polypropylene and polystyrene.
16. The electronic device as in claim 12 , wherein:
the first and second interfacial layers each comprise self-assembled monolayers such as: 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a-methylstyrene) or nanometer-thick layers of polymers such as polyethylene, polypropylene and polystyrene; and
the over-layer and under-layer each comprise SiO 2 , HfO 2 , Al 2 O 3 , Si 3 N 4 , Y 2 O 3 , PrO, GdO, La 2 O 3 , TiO, ZrO, AlN, BN, SiC; Ta 2 O 5 , SrTiO 3 , Ba x Sr 1-x , TiO 3 , Pb x Zr 1-x , or TiO 3 .
17. The electronic device as in claim 12 wherein the device is a field effect transistor.
18. The electronic device as in claim 12 wherein the device is a magnetoresistive sensor.